ATXMEGA256A3B-MH Atmel, ATXMEGA256A3B-MH Datasheet - Page 221

• Manufacturer Part Number: ATXMEGA256A3B-MH
• Description: MCU AVR 256KB FLASH A3B 64-QFN
• Manufacturer: Atmel
• Series: AVR® XMEGAr

Specifications of ATXMEGA256A3B-MH

• Core Processor: AVR
• Core Size: 8/16-Bit
• Speed: 32MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 49
• Program Memory Size: 256KB (128K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 3.6 V
• Data Converters: A/D 16x12b; D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-MLF®, 64-QFN
• Processor Series: ATXMEGA256x
• Core: AVR8
• Data Bus Width: 8 bit, 16 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, SPI, USART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 49
• Number Of Timers: 7
• Operating Supply Voltage: 1.6 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• On-chip Dac: 12 bit, 2 Channel
• For Use With: ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATSTK600 - DEV KIT FOR AVR/AVR32770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPI
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ATXMEGA256A3B-MU; ATXMEGA256A3B-MU

19.9.5
8077H–AVR–12/09
BAUD - TWI Baud Rate Register
• Bit 2 - BUSERR: Bus Error
The Bus Error (BUSERR) flag is set if an illegal bus condition has occurred. An illegal bus condi-
tion occurs if a Repeated START or STOP condition is detected, and the number of bits from the
previous START condition is not a multiple of nine. Writing a one to this bit location will clear the
BUSERR flag.
Writing the ADDR register will automatically clear the BUSERR flag.
• Bit 1:0 - BUSSTATE[1:0]: Bus State
The Bus State (BUSSTATE) bits indicate the current TWI bus state as defined in
The change of bus state is dependent on bus activity. Refer to the
Logic” on page
Table 19-5.
Writing 01 to the BUSSTATE bits forces the bus state logic into idle state. The bus state logic
cannot be forced into any other state. When the master is disabled, and after reset the Bus State
logic is disabled and the bus state is unknown.
The Baud Rate (BAUD) register defines the relation between the system clock and the TWI Bus
Clock (SCL) frequency. The frequency relation can be expressed by using the following
equation:
The BAUD register must be set to a value that results in a TWI bus clock frequency (f
or less 100 kHz or 400 kHz dependent on standard used by the application. The following equa-
tion [2] expresses equation [1] with respect to the BAUD value:
The BAUD register should be written while the master is disabled.
f
TWMBR
TWI
Bit
+0x04
Read/Write
Initial Value
=
BUSSTATE[1:0]
--------------------------------------- - [Hz]
2(5
=
+
------------- - 5
2f
00
01
10
11
f
TWMBR)
f
sys
TWI
sys
R/W
7
0
TWI master Bus State
212.
–
[2]
R/W
6
0
[1]
Group Configuration
UNKNOWN
R/W
5
0
OWNER
BUSY
IDLE
R/W
4
0
BAUD[7:0]
R/W
Description
Unknown Bus State
Idle
Owner
Busy
3
0
R/W
2
0
Section 19.4 ”TWI Bus State
R/W
1
0
XMEGA A
R/W
0
0
Table
TWI
) equal
BAUD
19-5.
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