ATXMEGA256A3B-MH Atmel, ATXMEGA256A3B-MH Datasheet - Page 201

• Manufacturer Part Number: ATXMEGA256A3B-MH
• Description: MCU AVR 256KB FLASH A3B 64-QFN
• Manufacturer: Atmel
• Series: AVR® XMEGAr

Specifications of ATXMEGA256A3B-MH

• Core Processor: AVR
• Core Size: 8/16-Bit
• Speed: 32MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 49
• Program Memory Size: 256KB (128K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 3.6 V
• Data Converters: A/D 16x12b; D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-MLF®, 64-QFN
• Processor Series: ATXMEGA256x
• Core: AVR8
• Data Bus Width: 8 bit, 16 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, SPI, USART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 49
• Number Of Timers: 7
• Operating Supply Voltage: 1.6 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• On-chip Dac: 12 bit, 2 Channel
• For Use With: ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATSTK600 - DEV KIT FOR AVR/AVR32770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPI
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ATXMEGA256A3B-MU; ATXMEGA256A3B-MU

18.3.6
18.3.7
18.3.8
18.3.9
8077H–AVR–12/09
CNT2 - Counter Register 2
CNT1 - Counter Register 1
CNT0 - Counter Register 0
PER3 - Period Register 3
PER3, PER2, PER1 and PER0 registers represent the 32-bit value PER. PER is constantly
compared with the counter value (CNT). A compare match will set the OVFIF in the INTFLAGS
register, and CNT will be set to zero in the next RTC clock cycle.
The PER register can only be written if the RTC is disabled and not currently synchronizing, i.e
when both ENABLE and SYNCBUSY are zero.
After writing a byte in the PER register the condition for setting OVFIF and the Overflow Wakeup
condition is disabled for the following two RTC clock cycles.
After reset this register is 0x0000, and it must be set to a value different that zero before the
enabled RTC starts counting.
Bit
+0x06
Read/Write
Reset Value
Bit
+0x05
Read/Write
Reset Value
Bit
+0x04
Read/Write
Reset Value
Bit
+0x0B
Read/Write
Reset Value
R/W
R/W
R/W
R/W
7
7
7
7
0
0
0
0
R/W
R/W
R/W
R/W
6
6
6
6
0
0
0
0
R/W
R/W
R/W
R/W
5
5
5
5
0
0
0
0
R/W
R/W
R/W
R/W
4
4
4
4
0
0
0
0
CNT[23:16]
PER[31:24]
CNT[15:8]
CNT[7:0]
R/W
R/W
R/W
R/W
3
3
3
3
0
0
0
0
R/W
R/W
R/W
R/W
2
2
2
2
0
0
0
0
R/W
R/W
R/W
R/W
1
1
1
1
0
0
0
0
XMEGA A
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
CNT2
CNT1
CNT0
PER3
201