ATXMEGA256A3B-MH Atmel, ATXMEGA256A3B-MH Datasheet - Page 14

• Manufacturer Part Number: ATXMEGA256A3B-MH
• Description: MCU AVR 256KB FLASH A3B 64-QFN
• Manufacturer: Atmel
• Series: AVR® XMEGAr

Specifications of ATXMEGA256A3B-MH

• Core Processor: AVR
• Core Size: 8/16-Bit
• Speed: 32MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 49
• Program Memory Size: 256KB (128K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 3.6 V
• Data Converters: A/D 16x12b; D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-MLF®, 64-QFN
• Processor Series: ATXMEGA256x
• Core: AVR8
• Data Bus Width: 8 bit, 16 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, SPI, USART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 49
• Number Of Timers: 7
• Operating Supply Voltage: 1.6 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• On-chip Dac: 12 bit, 2 Channel
• For Use With: ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATSTK600 - DEV KIT FOR AVR/AVR32770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPI
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ATXMEGA256A3B-MU; ATXMEGA256A3B-MU

3.14.3
3.14.4
3.14.5
8077H–AVR–12/09
RAMPX - Extended X-Pointer Register
RAMPY - Extended Y-Pointer Register
RAMPZ - Extended Z-Pointer Register
data addresses below 64K bytes, this register is not in use. This register is not available if the
data memory including external memory is less than 64K bytes.
• Bit 7:0 – RAMPD[7:0]: Extended Direct Addressing bits
These bits holds the 8 MSB of the 24-bit address created by RAMPD and the 16-bit operand.
Only the number of bits required to address the available data memory is implemented for each
device. Unused bits will always read as zero.
This register is concatenated with the X-register for indirect addressing (LD/LDD/ST/STD) of the
whole data memory space on devices with more than 64K bytes of data memory. When access-
ing data addresses below 64K bytes, this register is not in use. This register is not available if the
data memory including external memory is less than 64K bytes.
• Bit 7:0 – RAMPX[7:0]: Extended X-pointer Address bits
These bits holds the 8 MSB of the 24-bit address created by RAMPX and the 16-bit X-register.
Only the number of bits required to address the available data memory is implemented for each
device. Unused bits will always read as zero.
This register is concatenated with the Y-register for indirect addressing (LD/LDD/ST/STD) of the
whole data memory space on devices with more than 64K bytes of data memory. When access-
ing data addresses below 64K bytes, this register is not in use. This register is not available if the
data memory including external memory is less than 64K bytes.
• Bit 7:0 – RAMPY[7:0]: Extended Y-pointer Address bits
These bits hold the 8 MSB of the 24-bit address created by RAMPY and the 16-bit Y-register.
Only the number of bits required to address the available data memory is implemented for each
device. Unused bits will always read as zero.
This register is concatenated with the Z-register for indirect addressing (LD/LDD/ST/STD) of the
whole data memory space on devices with more than 64K bytes of data memory. RAMPZ is
concatenated with the Z-register when reading (ELPM) program memory locations above the
Bit
+0x0A
Read/Write
Initial Value
Bit
+0x09
Read/Write
Initial Value
Bit
+0x08
Read/Write
Initial Value
R/W
R/W
R/W
7
0
7
0
7
0
R/W
R/W
R/W
6
0
6
0
6
0
R/W
R/W
R/W
5
0
5
0
5
0
R/W
R/W
R/W
4
0
4
0
4
0
RAMPD[7:0]
RAMPX[7:0]
RAMPY[7:0]
R/W
R/W
R/W
3
0
3
0
3
0
R/W
R/W
R/W
2
0
2
0
2
0
R/W
R/W
R/W
1
0
1
0
1
0
XMEGA A
R/W
R/W
R/W
0
0
0
0
0
0
RAMPD
RAMPX
RAMPY
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