ATXMEGA256A3B-MH Atmel, ATXMEGA256A3B-MH Datasheet - Page 163

• Manufacturer Part Number: ATXMEGA256A3B-MH
• Description: MCU AVR 256KB FLASH A3B 64-QFN
• Manufacturer: Atmel
• Series: AVR® XMEGAr

Specifications of ATXMEGA256A3B-MH

• Core Processor: AVR
• Core Size: 8/16-Bit
• Speed: 32MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 49
• Program Memory Size: 256KB (128K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 3.6 V
• Data Converters: A/D 16x12b; D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-MLF®, 64-QFN
• Processor Series: ATXMEGA256x
• Core: AVR8
• Data Bus Width: 8 bit, 16 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, SPI, USART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 49
• Number Of Timers: 7
• Operating Supply Voltage: 1.6 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• On-chip Dac: 12 bit, 2 Channel
• For Use With: ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATSTK600 - DEV KIT FOR AVR/AVR32770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPI
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ATXMEGA256A3B-MU; ATXMEGA256A3B-MU

14.9
8077H–AVR–12/09
Interrupts and events
Figure 14-15. Port override for Timer/Counter 0 and 1
The T/C can generate both interrupts and events. The Counter can generate an interrupt on
overflow/underflow, and each CC channel has a separate interrupt that is used for compare or
capture. In addition the T/C can generate an error interrupt if any of the CC channels is used for
capture and a buffer overflow condition occurs on a capture channel.
Event will be generated for all conditions that can generate interrupts. For details on event gen-
eration and available events refer to
WG 0A
WG 0B
WG 0C
WG 0D
WG 1A
WG 1B
CCENA
CCENB
CCENC
CCEND
CCENA
CCENB
”Event System” on page
OUTx0
OUTx1
OUTx2
OUTx3
OUTx4
OUTx5
INVENx0
INVENx1
INVENx2
INVENx3
INVENx4
INVENx5
65.
OC0A
OC0B
OC0C
OC0D
OC1A
OC1B
Px0
Px1
Px2
Px3
Px4
Px5
XMEGA A
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