ATXMEGA256A3B-MH Atmel, ATXMEGA256A3B-MH Datasheet - Page 253

• Manufacturer Part Number: ATXMEGA256A3B-MH
• Description: MCU AVR 256KB FLASH A3B 64-QFN
• Manufacturer: Atmel
• Series: AVR® XMEGAr

Specifications of ATXMEGA256A3B-MH

• Core Processor: AVR
• Core Size: 8/16-Bit
• Speed: 32MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 49
• Program Memory Size: 256KB (128K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 3.6 V
• Data Converters: A/D 16x12b; D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-MLF®, 64-QFN
• Processor Series: ATXMEGA256x
• Core: AVR8
• Data Bus Width: 8 bit, 16 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, SPI, USART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 49
• Number Of Timers: 7
• Operating Supply Voltage: 1.6 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• On-chip Dac: 12 bit, 2 Channel
• For Use With: ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATSTK600 - DEV KIT FOR AVR/AVR32770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPI
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ATXMEGA256A3B-MU; ATXMEGA256A3B-MU

8077H–AVR–12/09
• Bits 5:4 - PMODE[1:0]: Parity Mode
These bits enable and set the type of parity generation according to
When enabled, the Transmitter will automatically generate and send the parity of the transmitted
data bits within each frame. The Receiver will generate a parity value for the incoming data and
compare it to the PMODE setting and if a mismatch is detected, the PERR flag in STATUS will
be set.
These bits are unused in Master SPI mode of operation.
Table 21-7.
• Bit 3 - SBMODE: Stop Bit Mode
This bit selects the number of stop bits to be inserted by the Transmitter according to
on page
This bit is unused in Master SPI mode of operation.
Table 21-8.
• Bit 2:0 - CHSIZE[2:0]: Character Size
The CHSIZE[2:0] bits sets the number of data bits in a frame according to
253. The Receiver and Transmitter use the same setting.
Table 21-9.
PMODE[1:0]
CHSIZE[2:0]
2. See
253. The Receiver ignores this setting.
000
001
010
011
100
101
110
111
00
01
10
11
PMODE Bits Settings
SBMODE Bit Settings
CHSIZE Bits Settings
”USART” on page 235
SBMODE
0
1
Group Configuration
Group Configuration
DISABLED
EVEN
ODD
5BIT
6BIT
7BIT
8BIT
9BIT
for full description of the Master SPI Mode (MSPIM) operation.
Parity mode
Disabled
Reserved
Enabled, Even Parity
Enabled, Odd Parity
Character size
5-bit
6-bit
7-bit
8-bit
Reserved
Reserved
Reserved
9-bit
Stop Bit(s)
1-bit
2-bit
Table 21-7 on page
Table 21-9 on page
XMEGA A
Table 21-8
253.
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