ATXMEGA256A3B-MH Atmel, ATXMEGA256A3B-MH Datasheet - Page 301

• Manufacturer Part Number: ATXMEGA256A3B-MH
• Description: MCU AVR 256KB FLASH A3B 64-QFN
• Manufacturer: Atmel
• Series: AVR® XMEGAr

Specifications of ATXMEGA256A3B-MH

• Core Processor: AVR
• Core Size: 8/16-Bit
• Speed: 32MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 49
• Program Memory Size: 256KB (128K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 3.6 V
• Data Converters: A/D 16x12b; D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-MLF®, 64-QFN
• Processor Series: ATXMEGA256x
• Core: AVR8
• Data Bus Width: 8 bit, 16 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, SPI, USART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 49
• Number Of Timers: 7
• Operating Supply Voltage: 1.6 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• On-chip Dac: 12 bit, 2 Channel
• For Use With: ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATSTK600 - DEV KIT FOR AVR/AVR32770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPI
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ATXMEGA256A3B-MU; ATXMEGA256A3B-MU

25.11 DMA transfer
25.12 Interrupts and events
25.13 Calibration
25.14 Channel priority
25.15 Synchronous sampling
8077H–AVR–12/09
where the ADC sample time, T
For details on R
teristic in the device data sheet.
The DMA Controller can be used to transfer ADC conversion results to memory or peripherals. A
new conversion completed in any of the ADC result registers may trigger a DMA transfer
request. See the DMA Controller manual for more details on DMA transfers.
The ADC can generate both interrupt requests and events. The ADC channels have individual
interrupt settings. Interrupt requests and events can be generated either when an ADC conver-
sion is complete or if an ADC measurement is above or below the ADC Compare register
values.
The ADC has a built-in calibration mechanism that calibrated the internal pipeline in the ADC.
The calibration value from the production test must be loaded from the signature row and into
the ADC calibration register from software to obtain 12 bit accuracy.
Since the System Clock can be faster than the ADC clock, it is possible to have the start conver-
sion bit set for several ADC channels within the same ADC clock period. Events may also trigger
conversions on several ADC channels and give the same scenario. In this case the ADC Chan-
nel with the lowest number will be prioritized. This is shown the timing diagrams in
and Conversion Timing” on page
Starting an ADC conversion may cause an unknown delay between the software start or event
and the actual conversion start since conversion of other higher priority ADC channels may be
pending, or since the System clock may be much faster than the ADC Clock. To start an ADC
conversion immediately on an incoming event, it is possible to flush the ADC for all measure-
ments, reset the ADC clock and start the conversion at the next Peripheral clock cycle, which
then will also be the next ADC clock cycle. If this is done all ongoing conversions in the ADC
pipeline will be lost. The ADC can either be flushed from software, or the incoming event can be
set up to do this automatically. If flushing is used it is important that the time between each con-
version start trigger is longer than the propagation delay to ensure that one conversion is
finished before the ADC pipeline is flushed and the next conversion is started.
In microcontrollers with two ADC peripherals, it is possible to start two ADC samples synchro-
nously in the two ADCs by using the same event channel to trigger both ADCs.
R
T
source
s
≤
-------------------
2 f ⋅
≤
1
ADC
---------------------------------------------- - R
C
sample
channel
⋅
T
ln
s
(
2
, R
n
+
1
switch
)
–
and C
channel
S
is one half ADC clock cycle given by:
296.
sample
–
R
switch
refer to the ADC and ADC gain stage electrical charac-
XMEGA A
”ADC Clock
301