ATXMEGA256A3B-MH Atmel, ATXMEGA256A3B-MH Datasheet - Page 252

• Manufacturer Part Number: ATXMEGA256A3B-MH
• Description: MCU AVR 256KB FLASH A3B 64-QFN
• Manufacturer: Atmel
• Series: AVR® XMEGAr

Specifications of ATXMEGA256A3B-MH

• Core Processor: AVR
• Core Size: 8/16-Bit
• Speed: 32MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 49
• Program Memory Size: 256KB (128K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 3.6 V
• Data Converters: A/D 16x12b; D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-MLF®, 64-QFN
• Processor Series: ATXMEGA256x
• Core: AVR8
• Data Bus Width: 8 bit, 16 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, SPI, USART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 49
• Number Of Timers: 7
• Operating Supply Voltage: 1.6 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• On-chip Dac: 12 bit, 2 Channel
• For Use With: ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATSTK600 - DEV KIT FOR AVR/AVR32770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPI
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ATXMEGA256A3B-MU; ATXMEGA256A3B-MU

21.15.5
8077H–AVR–12/09
CTRLC - USART Control Register C
• Bit 3 - TXEN: Transmitter Enable
Setting this bit enables the USART Transmitter. The Transmitter will override normal port opera-
tion for the TxD pin when enabled. Disabling the Transmitter (writing TXEN to zero) will not
become effective until ongoing and pending transmissions are completed, i.e., when the Trans-
mit Shift Register and Transmit Buffer Register do not contain data to be transmitted. When
disabled, the Transmitter will no longer override the TxD port.
• Bit 2 - CLK2X: Double Transmission Speed
Setting this bit will reduce the divisor of the baud rate divider from16 to 8 effectively doubling the
transfer rate for asynchronous communication modes. For synchronous operation this bit has no
effect and should always be written to zero. This bit must be zero when the USART Communica-
tion Mode is configured to IRCOM.
This bit is unused in Master SPI mode of operation.
• Bit 1 - MPCM: Multi-processor Communication Mode
This bit enables the Multi-processor Communication mode. When the MPCM bit is written to
one, the USART Receiver ignores all the incoming frames that do not contain address informa-
tion. The Transmitter is unaffected by the MPCM setting. For more detailed information see
”Multi-processor Communication Mode” on page
This bit is unused in Master SPI mode of operation.
• Bit 0 - TXB8: Transmit Bit 8
TXB8 is the ninth data bit in the character to be transmitted when operating with serial frames
with nine data bits. When used this bit must be written before writing the low bits to DATA.
This bit is unused in Master SPI mode of operation.
Note:
• Bits 7:6 - CMODE[1:0]: USART Communication Mode
These bits select the mode of operation of the USART as shown in
Table 21-6.
Notes:
Bit
+0x05
+0x05
Read/Write
Initial Value
(1)
CMODE[1:0]
1. Master SPI mode
1. See
00
01
10
11
using IRCOM mode.
7
CMODE bit settings
R/W
Section 22. ”IRCOM - IR Communication Module” on page 256
0
CMODE[1:0]
CMODE[1:0]
6
Group Configuration
R/W
ASYNCHRONOUS
0
SYNCHRONOUS
IRCOM
MSPI
5
R/W
0
-
PMODE[1:0]
4
R/W
Mode
Asynchronous USART
Synchronous USART
IRCOM
Master SPI
0
-
248.
(1)
3
SBMODE
R/W
(2)
0
-
2
UDORD
Table
R/W
1
for full description on
21-6.
1
CHSIZE[2:0]
XMEGA A
UCPHA
R/W
1
0
R/W
0
-
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