ATXMEGA256A3B-MH Atmel, ATXMEGA256A3B-MH Datasheet - Page 430

• Manufacturer Part Number: ATXMEGA256A3B-MH
• Description: MCU AVR 256KB FLASH A3B 64-QFN
• Manufacturer: Atmel
• Series: AVR® XMEGAr

Specifications of ATXMEGA256A3B-MH

• Core Processor: AVR
• Core Size: 8/16-Bit
• Speed: 32MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 49
• Program Memory Size: 256KB (128K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 3.6 V
• Data Converters: A/D 16x12b; D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-MLF®, 64-QFN
• Processor Series: ATXMEGA256x
• Core: AVR8
• Data Bus Width: 8 bit, 16 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, SPI, USART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 49
• Number Of Timers: 7
• Operating Supply Voltage: 1.6 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• On-chip Dac: 12 bit, 2 Channel
• For Use With: ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATSTK600 - DEV KIT FOR AVR/AVR32770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPI
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ATXMEGA256A3B-MU; ATXMEGA256A3B-MU

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8077H–AVR–12/09
8077F – 02/09
8077E – 01/09
8077D – 12/08
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Added ADC section
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Fuses and Lockbits” on page
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”STATUS: Battery Backup Status Register” on page
Table 9-2 on page
”Conversion Result” on page
”Overview” on page
”Capture Channel” on page
Figure 9-5
”Capture Channel” on page
”Production Signature Row” on page 20
”MCUCR – MCU Control Register” on page
”Interrupt Vector Summary - NVM Controller” on page
”Priority Between Channels” on page
”Manually Generating Events” on page 67
”Quadrature Decoder (QDEC)” on page
Figure 13-1 ”General I/O pin functionality.” on page
Table 13-7 ”Event Channel 0 output configurations” on page
Figure 13-10 ”Port override signals and related logic” on page
Table 13-7 on page
External reset characteristics in
”DAC Output model” on page
”Interrupt vector Summary” on page
”ADC Input Model” on page
”Event System” on page
”Memories” on page
”Battery Backup System” on page
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145: Event Channel 0 Output Configurations.
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Section 9.4.3 ”External reset” on page
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”Event Routing Network” on page
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Section 4.22 ”Register Summary -
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XMEGA A
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