ATXMEGA256A3B-MH Atmel, ATXMEGA256A3B-MH Datasheet - Page 265

• Manufacturer Part Number: ATXMEGA256A3B-MH
• Description: MCU AVR 256KB FLASH A3B 64-QFN
• Manufacturer: Atmel
• Series: AVR® XMEGAr

Specifications of ATXMEGA256A3B-MH

• Core Processor: AVR
• Core Size: 8/16-Bit
• Speed: 32MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 49
• Program Memory Size: 256KB (128K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 3.6 V
• Data Converters: A/D 16x12b; D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-MLF®, 64-QFN
• Processor Series: ATXMEGA256x
• Core: AVR8
• Data Bus Width: 8 bit, 16 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, SPI, USART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 49
• Number Of Timers: 7
• Operating Supply Voltage: 1.6 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• On-chip Dac: 12 bit, 2 Channel
• For Use With: ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATSTK600 - DEV KIT FOR AVR/AVR32770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPI
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ATXMEGA256A3B-MU; ATXMEGA256A3B-MU

23.5.2
23.5.3
8077H–AVR–12/09
STATUS - AES Status Register
STATE - AES State Register
• Bit 1:0 - Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always
write these bits to zero when this register is written.
• Bit 7 - ERROR: AES Error
The ERROR flag indicates an illegal handling of the AES Crypto Module. The flag is set in the
following cases:
This flag can be cleared by software by writing one to its bit location.
• Bit 6:1 - Reserved
These bits are reserved and will always be read as zero. For compatibility with future devices,
always write these bits to zero when this register is written.
• Bit 0 - SRIF: AES State Ready Interrupt flag
This flag is the interrupt/DMA request flag and is set when the encryption/decryption procedure
is completed and the State memory contains valid data. As long as the flag is zero this indicates
that there is no valid encrypted/decrypted data in the state memory.
The flag is cleared by hardware when a read access is made to the State memory (the first byte
is read). Alternatively the bit can be cleared by writing a one to its bit location
The State Register is used to access the State memory. Before encryption/decryption can take
place the State memory must be written sequentially byte by byte through the State Register.
After encryption/decryption is done the ciphertext/plaintext can be read sequentially byte by byte
through the State Register.
Loading the initial data to the State Register should be made after setting the appropriate AES-
mode and direction. During encryption/ decryption this register can not be accessed.
• Setting START in the Control Register while the State memory and/or Key memory are not
• Accessing (read or write) the Control Register while the START bit is one.
Bit
+0x01
Read/Write
Initial Value
fully loaded or read. This error occurs when the total number of read/write operations from/to
the State and Key register is not a multiple of 16 before an AES Start.
Bit
+0x02
Read/Write
Initial Value
ERROR
R
7
0
R/W
7
0
R
6
0
-
R/W
6
0
R
5
0
-
R/W
5
0
R
4
0
R/W
-
4
0
STATE
R
R/W
3
0
-
3
0
R/W
R
2
0
-
2
0
R/W
R
1
0
-
1
0
XMEGA A
SRIF
R/W
R
0
0
0
0
STATUS
STATE
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