ATXMEGA256A3B-MH Atmel, ATXMEGA256A3B-MH Datasheet - Page 217

• Manufacturer Part Number: ATXMEGA256A3B-MH
• Description: MCU AVR 256KB FLASH A3B 64-QFN
• Manufacturer: Atmel
• Series: AVR® XMEGAr

Specifications of ATXMEGA256A3B-MH

• Core Processor: AVR
• Core Size: 8/16-Bit
• Speed: 32MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 49
• Program Memory Size: 256KB (128K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 3.6 V
• Data Converters: A/D 16x12b; D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-MLF®, 64-QFN
• Processor Series: ATXMEGA256x
• Core: AVR8
• Data Bus Width: 8 bit, 16 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, SPI, USART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 49
• Number Of Timers: 7
• Operating Supply Voltage: 1.6 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• On-chip Dac: 12 bit, 2 Channel
• For Use With: ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATSTK600 - DEV KIT FOR AVR/AVR32770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPI
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ATXMEGA256A3B-MU; ATXMEGA256A3B-MU

19.8
19.8.1
19.9
19.9.1
8077H–AVR–12/09
Register Description - TWI
Register Description - TWI Master
CTRL– TWI Common Control Register
CTRLA - TWI Master Control Register A
• Bit 7:2 - Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always
write these bits to zero when this register is written.
• Bit 1
SCL.
• Bit 0 - EDIEN: External Driver Interface Enable
Setting this bit enables the use of the external driver interface, clearing this bit enables normal
two wire mode. See
Table 19-1.
• Bit 7:6 - INTLVL[1:0]: Interrupt Level
The Interrupt Level (INTLVL) bit select the interrupt level for the TWI master interrupts.
• Bit 5 - RIEN: Read Interrupt Enable
Setting the Read Interrupt Enable (RIEN) bit enables the Read Interrupt when the Read Interrupt
Flag (RIF) in the STATUS register is set. In addition the INTLVL bits must be unequal zero for
TWI master interrupts to be generated.
Setting this bit to one enables an internal hold time on SDA with respect to the negative edge of
Bit
+0x00
Read/Write
Initial Value
Bit
+0x00
Read/Write
Initial Value
EDIEN
0
1
- SDAHOLD: SDA Hold Time Enable.
Mode
Normal TWI
External Driver
Interface
R/W
7
R
0
7
0
-
External Driver Interface Enable
INTLVL[1:0]
Table 19-1
R/W
6
R
0
6
0
-
Comment
Two pin interface,
Slew rate control and input filter.
Four pin interface,
Standard I/O, no slew-rate control, no input filter.
for details.
RIEN
R/W
R
5
0
5
0
-
WIEN
R/W
R
4
0
4
0
-
ENABLE
R/W
R
3
0
3
0
-
R
R
2
0
2
0
-
-
SDAHOLD
R/W
R
1
0
1
0
-
XMEGA A
EDIEN
R/W
R
0
0
0
0
-
CTRLA
CTRL
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