ATXMEGA256A3B-MH Atmel, ATXMEGA256A3B-MH Datasheet - Page 126

• Manufacturer Part Number: ATXMEGA256A3B-MH
• Description: MCU AVR 256KB FLASH A3B 64-QFN
• Manufacturer: Atmel
• Series: AVR® XMEGAr

Specifications of ATXMEGA256A3B-MH

• Core Processor: AVR
• Core Size: 8/16-Bit
• Speed: 32MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 49
• Program Memory Size: 256KB (128K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 3.6 V
• Data Converters: A/D 16x12b; D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-MLF®, 64-QFN
• Processor Series: ATXMEGA256x
• Core: AVR8
• Data Bus Width: 8 bit, 16 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, SPI, USART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 49
• Number Of Timers: 7
• Operating Supply Voltage: 1.6 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• On-chip Dac: 12 bit, 2 Channel
• For Use With: ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATSTK600 - DEV KIT FOR AVR/AVR32770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPI
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ATXMEGA256A3B-MU; ATXMEGA256A3B-MU

12.6.2
8077H–AVR–12/09
Round-robin scheduling
Figure 12-1. Static priority.
To avoid the possible starvation problem for low level interrupts with static priority, the PMIC
gives the possibility for round-robin scheduling for low level interrupts. When round-robin sched-
uling is enabled, the interrupt vector address for the last acknowledged low level interrupt will
have the lowest priority next time one or more interrupts from the low level is requested.
Figure 12-2. Round-robin scheduling.
IV EC x las t ack now le dge d
inte rrupt
IV EC x+1
IV EC N
IV EC 0
IV EC x
:
:
:
:
:
:
Lowes t Addres s
Highes t Addres s
Low est Priority
Highest Priority
IVEC x+1
IVEC N
IVEC 0
IVEC x
:
:
:
:
:
:
IV EC x+1 las t ack now le dge d
inte rrupt
IV EC x+1
IV EC x+2
IV EC N
IV EC 0
IV EC x
Highes t Priority
Lowes t Priority
:
:
:
:
:
:
Low est Priority
Highest Priority
XMEGA A
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