ATXMEGA256A3B-MH Atmel, ATXMEGA256A3B-MH Datasheet - Page 98

• Manufacturer Part Number: ATXMEGA256A3B-MH
• Description: MCU AVR 256KB FLASH A3B 64-QFN
• Manufacturer: Atmel
• Series: AVR® XMEGAr

Specifications of ATXMEGA256A3B-MH

• Core Processor: AVR
• Core Size: 8/16-Bit
• Speed: 32MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 49
• Program Memory Size: 256KB (128K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 3.6 V
• Data Converters: A/D 16x12b; D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-MLF®, 64-QFN
• Processor Series: ATXMEGA256x
• Core: AVR8
• Data Bus Width: 8 bit, 16 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, SPI, USART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 49
• Number Of Timers: 7
• Operating Supply Voltage: 1.6 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• On-chip Dac: 12 bit, 2 Channel
• For Use With: ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATSTK600 - DEV KIT FOR AVR/AVR32770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPI
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ATXMEGA256A3B-MU; ATXMEGA256A3B-MU

8.6
8.6.1
8077H–AVR–12/09
Register Description – Power Reduction
PRGEN - General Power Reduction Register
Table 8-2.
• Bit 1 - SEN: Sleep Enable
This bit must be set to make the MCU enter the selected sleep mode when the SLEEP instruc-
tion is executed. To avoid unintentional entering of sleep modes, it is recommended to write
SEN just before executing the SLEEP instruction, and clearing it immediately after waking up.
• Bit 7:5 - Reserved
These bits are reserved and will always be read as zero. For compatibility with future devices,
always write these bits to zero when this register is written.
• Bit 4 - AES: AES Module
Setting this bit stops the clock to the AES module. When the bit is cleared the peripheral should
be reinitialized to ensure proper operation.
• Bit 3 - EBI: External Bus Interface
Setting this bit stops the clock to the External Bus Interface. When the bit is cleared the periph-
eral should be reinitialized to ensure proper operation. Note that the EBI is not present for all
devices.
• Bit 2 - RTC: Real-Time Counter
Setting this stops the clock to the Real Time Counter. When the bit is cleared the peripheral
should be reinitialized to ensure proper operation.
• Bit 1 - EVSYS: Event System
Setting this stops the clock to the Event System. When the bit is cleared the module will continue
like before the shutdown.
• Bit 0 - DMA: DMA Controller
Setting this stops the clock to the DMA Controller. This bit can only be set if the DMA Controller
is disabled.
Bit
+0x00
Read/Write
Initial Value
SMODE[2:0]
101
110
111
R
7
0
-
Sleep mode
R
6
0
-
SEN
1
1
1
R
5
0
-
AES
R/W
4
0
Group Configuration
ESTDBY
R/W
STDBY
EBI
3
0
-
RTC
R/W
2
0
EVSYS
R/W
Description
Reserved
Standby Mode
Extended Standby Mode
1
0
XMEGA A
DMA
R/W
0
0
PRGEN
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