ATXMEGA256A3B-MH Atmel, ATXMEGA256A3B-MH Datasheet - Page 349

• Manufacturer Part Number: ATXMEGA256A3B-MH
• Description: MCU AVR 256KB FLASH A3B 64-QFN
• Manufacturer: Atmel
• Series: AVR® XMEGAr

Specifications of ATXMEGA256A3B-MH

• Core Processor: AVR
• Core Size: 8/16-Bit
• Speed: 32MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 49
• Program Memory Size: 256KB (128K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 3.6 V
• Data Converters: A/D 16x12b; D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-MLF®, 64-QFN
• Processor Series: ATXMEGA256x
• Core: AVR8
• Data Bus Width: 8 bit, 16 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, SPI, USART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 49
• Number Of Timers: 7
• Operating Supply Voltage: 1.6 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• On-chip Dac: 12 bit, 2 Channel
• For Use With: ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATSTK600 - DEV KIT FOR AVR/AVR32770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPI
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ATXMEGA256A3B-MU; ATXMEGA256A3B-MU

29.3.6
29.3.6.1
29.3.7
8077H–AVR–12/09
Serial Reception
Direction Change
BREAK detector
Figure 29-8. Drive contention and collision detection on the PDI_DATA line
As long as the PDI transmits alternating ones and zeros, collisions cannot be detected because
the output driver will be active all the time preventing polling of the PDI_DATA line. However,
within a single frame the two stop bits should always be transmitted as ones, enabling collision
detection at least once per frame.
When a start bit is detected, the receiver starts to collect the eight data bits and shift them into
the shift register. If the parity bit does not correspond to the parity of the data bits, a parity error
has occurred. If one or both of the stop bits are low, a frame error has occurred. If the parity bit is
correct, and no frame error detected, the received data bits are parallelized and made available
for the PDI controller.
When the PDI is in TX-mode, a BREAK character signalized by the programmer will not be inter-
preted as a BREAK, but cause a generic data collision. When the PDI is in RX-mode, a BREAK
character will be recognized as a BREAK. By transmitting two successive BREAK characters
(must be separated by one or more high bits), the last BREAK character will always be recog-
nized as a BREAK, regardless of whether the PDI was in TX- or RX-mode initially.
In order to ensure correct timing of the half-duplex operation, a simple Guard Time mechanism
is added to the PDI physical interface during direction change. When the PDI changes from
operating in RX-mode to operate in TX-mode, a configurable number of additional IDLE bits are
inserted before the start bit is transmitted. The minimum transition time between RX- and TX-
mode is two IDLE cycles, and these are always inserted. Writing the Guard Time bits in the PDI
Controller’s Control Register specifies the additional Guard Time. The default Guard Time value
is +128 bits.
Programmer
PDI output
PDI_CLK
PDI_DATA
Collision
output
detect
= Collision
1
0
X
1
X
1
XMEGA A
1
349