ATXMEGA256A3B-MH Atmel, ATXMEGA256A3B-MH Datasheet - Page 53

• Manufacturer Part Number: ATXMEGA256A3B-MH
• Description: MCU AVR 256KB FLASH A3B 64-QFN
• Manufacturer: Atmel
• Series: AVR® XMEGAr

Specifications of ATXMEGA256A3B-MH

• Core Processor: AVR
• Core Size: 8/16-Bit
• Speed: 32MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 49
• Program Memory Size: 256KB (128K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 3.6 V
• Data Converters: A/D 16x12b; D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-MLF®, 64-QFN
• Processor Series: ATXMEGA256x
• Core: AVR8
• Data Bus Width: 8 bit, 16 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, SPI, USART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 49
• Number Of Timers: 7
• Operating Supply Voltage: 1.6 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• On-chip Dac: 12 bit, 2 Channel
• For Use With: ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATSTK600 - DEV KIT FOR AVR/AVR32770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPI
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ATXMEGA256A3B-MU; ATXMEGA256A3B-MU

5.13
5.13.1
8077H–AVR–12/09
Register Description – DMA Controller
CTRL - DMA Control Register
• Bit 7 - ENABLE: DMA Enable
Setting this bit enables the DMA Controller. If the DMA Controller is enabled and this bit is writ-
ten to zero, the ENABLE bit is not cleared before the internal transfer buffer is empty and the
DMA data transfer is aborted.
• Bit 6 - RESET: DMA Software Reset
Setting this bit enables the software reset. This bit is automatically cleared when reset is com-
pleted. This bit can only be set when the DMA Controller is disabled (ENABLE = 0).
• Bit 5:4 - Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always
write these bits to zero when this register is written.
• Bit 3:2 - DBUFMODE[1:0]: DMA Double Buffer Mode
These bits enables the double buffer on the different channels according to
Table 5-1.
• Bit 1:0 - PRIMODE[1:0]: DMA Channel Priority Mode
These bits determine the internal channel priority according to
Table 5-2.
Bit
+0x00
Read/Write
Initial Value
DBUFMODE[1:0]
PRIMODE[1:0]
00
01
10
11
00
01
10
11
ENABLE
R/W
DMA Double Buffer settings
DMA Channel Priority settings
7
0
Group Configuration
Group Configuration
RESET
R/W
6
0
CH0RR123
CH01RR23
CH01CH23
DISABLED
RR0123
CH0123
CH01
CH23
R
5
0
-
4
R
0
-
Description
Round Robin
Channel0 > Round Robin (Channel 1, 2 and 3)
Channel0 > Channel1 > Round Robin (Channel 2 and
3)
Channel0 > Channel1 > Channel2 > Channel3
Description
No double buffer enabled
Double buffer enabled on channel0/1
Double buffer enabled on channel2/3
Double buffer enabled on channel0/1 and channel2/3
R/W
DBUFMODE[1:0]
3
0
R/W
2
0
Table
5-2.
R/W
1
0
PRIMODE[1:0]
Table
XMEGA A
R/W
0
0
5-1.
CTRL
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