ATXMEGA256A3B-MH Atmel, ATXMEGA256A3B-MH Datasheet - Page 142

• Manufacturer Part Number: ATXMEGA256A3B-MH
• Description: MCU AVR 256KB FLASH A3B 64-QFN
• Manufacturer: Atmel
• Series: AVR® XMEGAr

Specifications of ATXMEGA256A3B-MH

• Core Processor: AVR
• Core Size: 8/16-Bit
• Speed: 32MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 49
• Program Memory Size: 256KB (128K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 3.6 V
• Data Converters: A/D 16x12b; D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-MLF®, 64-QFN
• Processor Series: ATXMEGA256x
• Core: AVR8
• Data Bus Width: 8 bit, 16 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, SPI, USART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 49
• Number Of Timers: 7
• Operating Supply Voltage: 1.6 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• On-chip Dac: 12 bit, 2 Channel
• For Use With: ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATSTK600 - DEV KIT FOR AVR/AVR32770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPI
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ATXMEGA256A3B-MU; ATXMEGA256A3B-MU

13.14.13 INTFLAGS - Interrupt Flag Register
13.14.14 PINnCTRL - Pin n Configuration Register
8077H–AVR–12/09
• Bit 7:2 - Reserved
These bits are reserved and will always be read as zero. For compatibility with future devices,
always write these bits to zero when this register is written.
• Bit 1:0 - INTnIF: Interrupt n Flag
The INTnIF flag is set when a pin change according to the pin's input sense configuration
occurs, and the pin is set as source for port interrupt n. Writing a one to this flag's bit location will
clear the flag. For enabling and executing the interrupt refer to the interrupt level description.
• Bit 7 - SRLEN: Slew Rate Limit Enable
Setting this bit will enable slew-rate limiting on pin n.
• Bit 6 - INVEN: Inverted I/O Enable
Setting this bit will enable inverting output and input data on pin n.
• Bit 5:3 - OPC: Output and Pull Configuration
These bits set the Output/Pull configuration on pin n according to
Table 13-4.
Bit
Read/Write
Initial Value
Bit
+0x0C
Read/Write
Initial Value
OPC[2:0]
000
001
010
011
100
101
110
111
SRLEN
R/W
7
R
0
7
0
-
Output/Pull Configuration
Group Configuration
TOTEM
BUSKEEPER
PULLDOWN
PULLUP
WIREDOR
WIREDAND
WIREDORPULL
WIREDANDPULL
INVEN
R/W
6
R
0
6
0
-
R/W
R
5
0
5
0
-
OPC[2:0]
R/W
R
4
0
4
0
-
Output configuration
Totempole
Totempole
Totempole
Totempole
Wired OR
Wired AND
Wired OR
Wired AND
R/W
R
3
0
3
0
-
R/W
R
2
0
2
0
-
Description
Table
ISC[2:0]
INT1IF
R/W
R/W
1
0
1
0
Pull configuration
(N/A)
Bus keeper
Pull-down (on input)
Pull-up (on input)
(N/A)
(N/A)
Pull-down
Pull-up
13-4.
XMEGA A
INT0IF
R/W
R/W
0
0
0
0
INTFLAGS
PINnCTRL
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