ATXMEGA256A3B-MH Atmel, ATXMEGA256A3B-MH Datasheet - Page 132

• Manufacturer Part Number: ATXMEGA256A3B-MH
• Description: MCU AVR 256KB FLASH A3B 64-QFN
• Manufacturer: Atmel
• Series: AVR® XMEGAr

Specifications of ATXMEGA256A3B-MH

• Core Processor: AVR
• Core Size: 8/16-Bit
• Speed: 32MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 49
• Program Memory Size: 256KB (128K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 3.6 V
• Data Converters: A/D 16x12b; D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-MLF®, 64-QFN
• Processor Series: ATXMEGA256x
• Core: AVR8
• Data Bus Width: 8 bit, 16 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, SPI, USART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 49
• Number Of Timers: 7
• Operating Supply Voltage: 1.6 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• On-chip Dac: 12 bit, 2 Channel
• For Use With: ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATSTK600 - DEV KIT FOR AVR/AVR32770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPI
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ATXMEGA256A3B-MU; ATXMEGA256A3B-MU

13.4.1.2
13.4.2
13.4.3
8077H–AVR–12/09
Bus-keeper
Wired-OR
Totem-pole with Pull-up
In this mode, the configuration is as for Totem-pole, expect the pin is configured with internal
pull-up when set as input.
Figure 13-4. I/O pin configuration - Totem-pole with pull-up (on input).
When the pin is configured for bus-keeper, it provides a weak bus-keeper that will keep the pin
at its logic level when the pin is no longer driven to any logic state. If last level on the pin/bus was
1, the bus-keeper will use the internal pull resistor to keep the bus high. If last logic level on the
pin/bus was 0, the bus-keeper will use the internal pull resistor to keep the bus high.
The bus-keeper’s week output produces the same logical level as the last output level. It acts as
a pull-up if the last level was '1', and pull-down if the last level was '0'.
Figure 13-5. I/O pin configuration - Totem-pole with bus-keeper
With Wired-OR configuration, the pin will be driven high when the corresponding bit in OUT is
written to one. When OUT is set to zero, the pin is released allowing the pin to be pulled low with
the internal or an external pull-resistor. If internal pull-down is used, this is also active if the pin is
set as input.
OUTn
OUTn
DIRn
DIRn
INn
INn
Pn
Pn
XMEGA A
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