ATXMEGA256A3B-MH Atmel, ATXMEGA256A3B-MH Datasheet - Page 83

• Manufacturer Part Number: ATXMEGA256A3B-MH
• Description: MCU AVR 256KB FLASH A3B 64-QFN
• Manufacturer: Atmel
• Series: AVR® XMEGAr

Specifications of ATXMEGA256A3B-MH

• Core Processor: AVR
• Core Size: 8/16-Bit
• Speed: 32MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 49
• Program Memory Size: 256KB (128K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 3.6 V
• Data Converters: A/D 16x12b; D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-MLF®, 64-QFN
• Processor Series: ATXMEGA256x
• Core: AVR8
• Data Bus Width: 8 bit, 16 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, SPI, USART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 49
• Number Of Timers: 7
• Operating Supply Voltage: 1.6 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• On-chip Dac: 12 bit, 2 Channel
• For Use With: ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATSTK600 - DEV KIT FOR AVR/AVR32770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPI
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ATXMEGA256A3B-MU; ATXMEGA256A3B-MU

8077H–AVR–12/09
clock or oscillator is used to derive the System Clock (i.e clock reference for the PLL when this is
used as the active system clock) and an clock or oscillator fails (stops), the device will:
If the external oscillator fails when it is not used as the System Clock source, the external oscil-
lator is automatically disabled while the system clock will continue to operate normally.
If the external clock is below 32 kHz then the failure monitor mechanism should not be enabled
in order to avoid unintentional fail detection.
When the failure monitor is enabled, it cannot be disabled until next reset.
The failure monitor is automatically disabled in all sleep modes where the external clock or oscil-
lator is stopped. During wake-up from sleep it is automatically enabled again.
The External Clock Source Failure Monitor setting is protected by the Configuration Change Pro-
tection mechanism, employing a timed write procedure for changing the system clock and
prescaler settings. For details refer to
• Switch to the 2 MHz internal oscillator, independently of any clock system lock setting.
• Reset the Oscillator Control Register and System Clock Selection Register to their default
• Set the External Clock Source Failure Detection Interrupt Flag.
• Issue a non-maskable interrupt (NMI).
values.
”Configuration Change Protection” on page
XMEGA A
12.
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