ATXMEGA256A3B-MH Atmel, ATXMEGA256A3B-MH Datasheet - Page 254

• Manufacturer Part Number: ATXMEGA256A3B-MH
• Description: MCU AVR 256KB FLASH A3B 64-QFN
• Manufacturer: Atmel
• Series: AVR® XMEGAr

Specifications of ATXMEGA256A3B-MH

• Core Processor: AVR
• Core Size: 8/16-Bit
• Speed: 32MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 49
• Program Memory Size: 256KB (128K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 3.6 V
• Data Converters: A/D 16x12b; D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-MLF®, 64-QFN
• Processor Series: ATXMEGA256x
• Core: AVR8
• Data Bus Width: 8 bit, 16 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, SPI, USART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 49
• Number Of Timers: 7
• Operating Supply Voltage: 1.6 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• On-chip Dac: 12 bit, 2 Channel
• For Use With: ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATSTK600 - DEV KIT FOR AVR/AVR32770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPI
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ATXMEGA256A3B-MU; ATXMEGA256A3B-MU

21.15.6
21.15.7
8077H–AVR–12/09
BAUDCTRLA - USART Baud Rate Register
BAUDCTRLB - USART Baud Rate Register
• Bit 2 - UDORD: Data Order
This bit sets the frame format. When written to one the LSB of the data word is transmitted first.
When written to zero the MSB of the data word is transmitted first. The Receiver and Transmitter
use the same setting. Changing the setting of UDORD will corrupt all ongoing communication for
both receiver and transmitter.
• Bit 1 - UCPHA: Clock Phase
The UCPHA bit setting determine if data is sampled on the leading (first) edge or tailing (last)
edge of XCKn. Refer to the
• Bit 7:0 - BSEL[7:0]: USART Baud Rate Register
This is a 12-bit value which contains the USART baud rate setting. The BAUDCTRLB contains
the four most significant bits, and the BAUDCTRLA contains the eight least significant bits of the
USART baud rate. Ongoing transmissions by the Transmitter and Receiver will be corrupted if
the baud rate is changed. Writing BAUDCTRLA will trigger an immediate update of the baud rate
prescaler.
• Bit 7:4 - BSCALE[3:0]: USART Baud Rate Scale factor
These bits select the Baud Rate Generator scale factor. The scale factor is given in two's com-
plement form from -7 (0b1001) to 7 (0b0111). The -8 (0b1000) setting is reserved. For positive
scale values the Baud Rate Generator is prescaled by 2
Rate Generator will use fractional counting, which increases the resolution. See equations in
Table 21-1 on page
• Bit 3:0 - BSEL[3:0]: USART Baud Rate Register
This is a 12-bit value which contains the USART baud rate setting. The BAUDCTRLB contains
the four most significant bits, and the BAUDCTRLA contains the eight least significant bits of the
USART baud rate. Ongoing transmissions by the Transmitter and Receiver will be corrupted if
the baud rate is changed. Writing BAUDCTRLA will trigger an immediate update of the baud rate
prescaler.
Bit
+0x07
Read/Write
Initial Value
Bit
+0x06
Read/Write
Initial Value
R/W
R/W
7
0
7
0
238.
R/W
R/W
6
0
6
0
BSCALE[3:0]
”SPI Clock Generation” on page 239
R/W
R/W
5
0
5
0
R/W
R/W
4
0
4
0
BSEL[7:0]
R/W
R/W
3
0
3
0
BSCALE
R/W
R/W
2
0
2
0
BSEL[11:8]
. For negative values the Baud
for details.
R/W
R/W
1
0
1
0
XMEGA A
R/W
R/W
0
0
0
0
BAUDCTRLA
BAUDCTRLB
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