ATXMEGA256A3B-MH Atmel, ATXMEGA256A3B-MH Datasheet - Page 266

• Manufacturer Part Number: ATXMEGA256A3B-MH
• Description: MCU AVR 256KB FLASH A3B 64-QFN
• Manufacturer: Atmel
• Series: AVR® XMEGAr

Specifications of ATXMEGA256A3B-MH

• Core Processor: AVR
• Core Size: 8/16-Bit
• Speed: 32MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 49
• Program Memory Size: 256KB (128K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 3.6 V
• Data Converters: A/D 16x12b; D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-MLF®, 64-QFN
• Processor Series: ATXMEGA256x
• Core: AVR8
• Data Bus Width: 8 bit, 16 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, SPI, USART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 49
• Number Of Timers: 7
• Operating Supply Voltage: 1.6 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• On-chip Dac: 12 bit, 2 Channel
• For Use With: ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATSTK600 - DEV KIT FOR AVR/AVR32770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPI
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ATXMEGA256A3B-MU; ATXMEGA256A3B-MU

23.5.4
23.5.5
8077H–AVR–12/09
KEY - AES Key Register
INTCTRL - AES Interrupt Control Register
The Key Register is used to access the Key memory. Before encryption/decryption can take
place the Key memory must be written sequentially byte by byte through the Key Register. After
encryption/decryption is done the last subkey can be read sequentially byte by byte through the
Key Register.
Loading the initial data to the Key Register should be made after setting the appropriate AES-
mode and direction.
These bits are unused and reserved for future use. For compatibility with future devices, always
write these bits to zero when this register is written.
These bits enable the AES Interrupt and select the interrupt level as described in
”Interrupts and Programmable Multi-level Interrupt Controller” on page
rupt will be triggered when the SRIF in the STATUS register is set.
Bit
+0x04
Read/Write
Initial Value
Bit
+0x03
Read/Write
Initial Value
• Bit 7:2 - Reserved
• Bit 1:0 - INTLVL[1:0]: AES Interrupt priority and enable
R/W
7
R
0
-
7
0
R/W
R
6
0
-
6
0
R/W
R
5
0
-
5
0
R/W
R
4
0
-
4
0
KEY
R/W
R
3
0
-
3
0
R/W
2
R
0
-
2
0
R/W
R/W
1
0
1
0
INTLVL[1:0]
123. The enabled inter-
XMEGA A
R/W
R/W
0
0
0
0
Section 12.
INTCTRL
KEY
266