ATXMEGA256A3B-MH Atmel, ATXMEGA256A3B-MH Datasheet - Page 114

• Manufacturer Part Number: ATXMEGA256A3B-MH
• Description: MCU AVR 256KB FLASH A3B 64-QFN
• Manufacturer: Atmel
• Series: AVR® XMEGAr

Specifications of ATXMEGA256A3B-MH

• Core Processor: AVR
• Core Size: 8/16-Bit
• Speed: 32MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 49
• Program Memory Size: 256KB (128K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 3.6 V
• Data Converters: A/D 16x12b; D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-MLF®, 64-QFN
• Processor Series: ATXMEGA256x
• Core: AVR8
• Data Bus Width: 8 bit, 16 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, SPI, USART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 49
• Number Of Timers: 7
• Operating Supply Voltage: 1.6 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• On-chip Dac: 12 bit, 2 Channel
• For Use With: ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATSTK600 - DEV KIT FOR AVR/AVR32770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPI
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ATXMEGA256A3B-MU; ATXMEGA256A3B-MU

10.6
10.6.1
8077H–AVR–12/09
Register Description
CTRL: Battery Backup Control Register
1. Set the ACCEN bit and apply a RESET
1. Enable the Crystal oscillator.
2. Wait until Crystal Oscillator ready flag is set.
3. Enable XOSC Fault Detection.
4. Configure and enable the RTC32.
• Bit [7:5] - Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always
write these bits to zero when this register is written.
• Bit 4- XOSCSEL: 32-kHz Crystal Oscillator Output Selection
This bit selects which clock output from the 32.768 kHz crystal oscillator that will be used as
clock input for the 32-bit Real Time Counter (RTC).
By default this bit is zero, and the 1 Hz clock output is used as input for the RTC. Setting this bit
will select the 1.024 kHz clock output as input for the RTC. The Crystal Oscillator must be
enabled before the output is available. This bit cannot be changed when XOSCEN is set.
• Bit 3- XOSCEN: Crystal Oscillator Enable
Setting this bit will enable the 32.768 kHz crystal oscillator, and thSetting this bite default 1 Hz
output from the oscillator. Writing the bit to zero will have no effect. The oscillator will remain
enabled until a Battery Backup RESET is issued.
• Bit 2- XOSCFDEN: Crystal Oscillator Failure DSetting this bitetection Enable
Setting this bit will enable the 32.768 kHz crystal oscillator monitor. Writing the bit to zero will
have no effect. When enabled, the Crystal Oscillator Monitor will remain enabled until a Battery
Backup RESET is issued.
• Bit 1- ACCEN: Battery Backup Module Access Enable
Setting this bit will enable access to the Battery Backup Module. After main reset this bit must be
set in order to access (read from and write to) the battery backup domain functions and register
settings, except for the BBPODF, the BBBODF and the BBPWR flag.
• Bit 0- RESET: Battery Backup Reset
Setting this bit will force a reset of the Battery Backup Module. Writing the bit to zero will have no
effect. Writing a one to the XOSCEN or the XOSCFDEN bit the same time will block writing to
this bit. When this bit is set XOSCEN, XOSCFDEN, XOSCSEL, and XOSCRDY in STATUS will
be cleared.
Bit
+0x00
Read/Write
Reset Value
7
-
R
0
6
-
R
0
5
-
R
0
XOSCSEL
R/W
4
0
XOSCEN
R/W
3
0
XOSCFDEN
R/W
2
0
ACCEN
R/W
1
0
RESET
XMEGA A
R/W
0
0
CTRL
114