ATXMEGA256A3B-MH Atmel, ATXMEGA256A3B-MH Datasheet - Page 321

• Manufacturer Part Number: ATXMEGA256A3B-MH
• Description: MCU AVR 256KB FLASH A3B 64-QFN
• Manufacturer: Atmel
• Series: AVR® XMEGAr

Specifications of ATXMEGA256A3B-MH

• Core Processor: AVR
• Core Size: 8/16-Bit
• Speed: 32MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 49
• Program Memory Size: 256KB (128K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 3.6 V
• Data Converters: A/D 16x12b; D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-MLF®, 64-QFN
• Processor Series: ATXMEGA256x
• Core: AVR8
• Data Bus Width: 8 bit, 16 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, SPI, USART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 49
• Number Of Timers: 7
• Operating Supply Voltage: 1.6 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• On-chip Dac: 12 bit, 2 Channel
• For Use With: ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATSTK600 - DEV KIT FOR AVR/AVR32770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPI
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ATXMEGA256A3B-MU; ATXMEGA256A3B-MU

26.10.3
8077H–AVR–12/09
CTRLC – DAC Control Register C
Table 26-1.
• Bits 4:2 - Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always
write these bits to zero when this register is written.
• Bit 1 - CH1TRIG: DAC Auto trigged mode Channel 1
If this bit is set, the incoming event on the event channel selected in the EVCTRL Register will
start the conversion when a new value is written to high byte of the data register CH1DATA.
• Bit 0 - CH0TRIG: DAC Auto trigged mode Channel 0
If this bit is set, the incoming event on the event channel selected in the EVCTRL Register will
start the conversion when a new value is written to high byte of the data register CH0DATA.
• Bits 7:5 - Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always
write these bits to zero when this register is written.
• Bits 4:3 - REFSEL[1:0]: DAC Reference Selection
These bits control the reference and thus the conversion range of the DAC.
Table 26-2
Table 26-2.
• Bit 2:1 - Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always
write these bits to zero when this register is written.
Bit
+0x02
Read/Write
Initial Value
CHSEL[1:0]
REFSEL[1:0]
00
01
10
11
00
01
10
11
shows the available options.
R
7
0
-
DAC channel selection
DAC Reference selection
Description
Single channel operation (for channel 0 only)
Reserved
Duel channel operation (S/H for channel 0 and channel 1)
Reserved
R
6
0
-
Group Configuration
AREFB
AREFA
R
INT1V
5
0
AVCC
-
R/W
4
0
REFSEL[1:0]
R/W
3
0
R/W
2
0
-
AREF on PORTB
AREF on PORTA
Internal 1.00 V
Description
AV
R/W
1
0
-
CC
XMEGA A
LEFTADJ
R/W
0
0
CTRLC
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