ATXMEGA256A3B-MH Atmel, ATXMEGA256A3B-MH Datasheet - Page 86

• Manufacturer Part Number: ATXMEGA256A3B-MH
• Description: MCU AVR 256KB FLASH A3B 64-QFN
• Manufacturer: Atmel
• Series: AVR® XMEGAr

Specifications of ATXMEGA256A3B-MH

• Core Processor: AVR
• Core Size: 8/16-Bit
• Speed: 32MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 49
• Program Memory Size: 256KB (128K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 3.6 V
• Data Converters: A/D 16x12b; D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-MLF®, 64-QFN
• Processor Series: ATXMEGA256x
• Core: AVR8
• Data Bus Width: 8 bit, 16 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, SPI, USART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 49
• Number Of Timers: 7
• Operating Supply Voltage: 1.6 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• On-chip Dac: 12 bit, 2 Channel
• For Use With: ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATSTK600 - DEV KIT FOR AVR/AVR32770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPI
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ATXMEGA256A3B-MU; ATXMEGA256A3B-MU

7.9.3
7.9.4
8077H–AVR–12/09
LOCK - Clock System Lock Register
RTCCTRL - RTC Control Register
• Bit 7:1 - Reserved
These bits are reserved and will always be read as zero. For compatibility with future devices,
always write these bits to zero when this register is written.
• Bit 0 - LOCK: Clock System Lock
When the LOCK bit is written to one the CTRL and PSCTRL registers cannot be changed, and
the system clock selection and prescaler settings is protected against all further updates until
after the next reset. This bits are protected by the Configuration Change Protection mechanism,
for details refer to
The LOCK bit will only be cleared by a system reset.
• Bit 7:4 - Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always
write these bits to zero when this register is written.
• Bit 3:1 - RTCSRC[2:0]: Clock Source
These bits select the clock source for the Real Time Counter according to
Table 7-4.
Bit
+0x03
Read/Write
Initial Value
Bit
+0x02
Read/Write
Initial Value
RTCSRC[2:0]
000
001
010
011
100
101
110
111
7
R
0
-
R
7
0
-
RTC Clock Source
Section 3.12 ”Configuration Change Protection” on page
Group Configuration
6
R
0
-
R
6
0
-
TOSC32
RCOSC
TOSC
ULP
-
-
-
-
R
5
0
-
R
5
0
-
R
4
0
-
R
4
0
-
Description
1 kHz from internal 32 kHz ULP
1.024 kHz from 32.768 kHz Crystal Oscillator on TOSC
1.024 kHz from internal 32.768 kHz RC Oscillator
Reserved
Reserved
32.768 kHz from 32.768 kHz Crystal Oscillator on TOSC
Reserved
Reserved
R/W
3
0
R
3
0
-
RTCSRC[2:0]
R/W
2
0
R
2
0
-
R/W
1
0
R
1
0
-
Table
12.
XMEGA A
RTCEN
R/W
LOCK
0
0
R/W
7-4..
0
0
RTCCTRL
LOCK
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