ATXMEGA256A3B-MH Atmel, ATXMEGA256A3B-MH Datasheet - Page 355

• Manufacturer Part Number: ATXMEGA256A3B-MH
• Description: MCU AVR 256KB FLASH A3B 64-QFN
• Manufacturer: Atmel
• Series: AVR® XMEGAr

Specifications of ATXMEGA256A3B-MH

• Core Processor: AVR
• Core Size: 8/16-Bit
• Speed: 32MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 49
• Program Memory Size: 256KB (128K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 3.6 V
• Data Converters: A/D 16x12b; D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-MLF®, 64-QFN
• Processor Series: ATXMEGA256x
• Core: AVR8
• Data Bus Width: 8 bit, 16 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, SPI, USART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 49
• Number Of Timers: 7
• Operating Supply Voltage: 1.6 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• On-chip Dac: 12 bit, 2 Channel
• For Use With: ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATSTK600 - DEV KIT FOR AVR/AVR32770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPI
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ATXMEGA256A3B-MU; ATXMEGA256A3B-MU

29.5.6.2
29.5.6.3
29.5.6.4
29.5.6.5
29.5.6.6
8077H–AVR–12/09
STS - Store data to PDIBUS Data Space using direct addressing
LD - Load data from PDIBUS Data Space using indirect addressing
ST - Store data to PDIBUS Data Space using indirect addressing
LDCS - Load data from PDI Control and Status Register Space
STCS - Store data to PDI Control and Status Register Space
address/data sizes are supported; byte, word, 3 bytes, and long (4 bytes). It should be noted that
multiple-bytes access is internally broken down to repeated single-byte accesses. The main
advantage with the multiple-bytes access is that it gives a way to reduce the protocol overhead.
When using the LDS, the address byte(s) must be transmitted before the data transfer.
The ST instruction is used to store data that is serially shifted into the physical layer shift-register
to locations within the PDIBUS Data Space. The STS instruction is based on direct addressing,
which means that the address must be given as an argument to the instruction. Even though the
protocol is based on byte-wise communication, the ST instruction supports multiple-bytes
address - and data access. Four different address/data sizes are supported; byte, word, 3 bytes,
and long (4 bytes). It should be noted that multiple-bytes access is internally broken down to
repeated single-byte accesses. The main advantage with the multiple-bytes access is that it
gives a way to reduce the protocol overhead. When using the STS, the address byte(s) must be
transmitted before the data transfer.
The LD instruction is used to load data from the PDIBUS Data Space to the physical layer shift-
register for serial read-out. The LD instruction is based on indirect addressing (pointer access),
which means that the address must be stored into the Pointer register prior to the data access.
Indirect addressing can be combined with pointer increment. In addition to read data from the
PDIBUS Data Space, the Pointer register can be read by the LD instruction. Even though the
protocol is based on byte-wise communication, the LD instruction supports multiple-bytes
address - and data access. Four different address/data sizes are supported; byte, word, 3 bytes,
and long (4 bytes). It should be noted that multiple-bytes access is internally broken down to
repeated single-byte accesses. The main advantage with the multiple-bytes access is that it
gives a way to reduce the protocol overhead.
The ST instruction is used to store data that is serially shifted into the physical layer shift-register
to locations within the PDIBUS Data Space. The ST instruction is based on indirect addressing
(pointer access), which means that the address must be stored into the Pointer register prior to
the data access. Indirect addressing can be combined with pointer increment. In addition to write
data to the PDIBUS Data Space, the Pointer register can be written by the ST instruction. Even
though the protocol is based on byte-wise communication, the ST instruction supports multiple-
bytes address - and data access. Four different address/data sizes are supported; byte, word, 3
bytes, and long (4 bytes). It should be noted that multiple-bytes access is internally broken down
to repeated single-byte accesses. The main advantage with the multiple-bytes access is that it
gives a way to reduce the protocol overhead.
The LDCS instruction is used to load data from the PDI Control and Status Registers to the
physical layer shift-register for serial read-out. The LDCS instruction supports only direct
addressing and single-byte access.
The STCS instruction is used to store data that is serially shifted into the physical layer shift-reg-
ister to locations within the PDI Control and Status Registers. The STCS instruction supports
only direct addressing and single-byte access.
XMEGA A
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