ATXMEGA256A3B-MH Atmel, ATXMEGA256A3B-MH Datasheet - Page 248

• Manufacturer Part Number: ATXMEGA256A3B-MH
• Description: MCU AVR 256KB FLASH A3B 64-QFN
• Manufacturer: Atmel
• Series: AVR® XMEGAr

Specifications of ATXMEGA256A3B-MH

• Core Processor: AVR
• Core Size: 8/16-Bit
• Speed: 32MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 49
• Program Memory Size: 256KB (128K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 3.6 V
• Data Converters: A/D 16x12b; D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-MLF®, 64-QFN
• Processor Series: ATXMEGA256x
• Core: AVR8
• Data Bus Width: 8 bit, 16 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, SPI, USART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 49
• Number Of Timers: 7
• Operating Supply Voltage: 1.6 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• On-chip Dac: 12 bit, 2 Channel
• For Use With: ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATSTK600 - DEV KIT FOR AVR/AVR32770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPI
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ATXMEGA256A3B-MU; ATXMEGA256A3B-MU

21.12 Multi-processor Communication Mode
21.12.1
8077H–AVR–12/09
Using Multi-processor Communication Mode
A comparison of the USART in Master SPI mode and the SPI pins is shown
Table 21-5.
Enabling the Multi-processor Communication Mode (MPCM) effectively reduces the number of
incoming frames that has to be handled by the Receiver in a system with multiple MCUs com-
municating via the same serial bus. In this mode a dedicated bit in the frames is used to indicate
whether the frame is an address or data frame.
If the Receiver is set up to receive frames that contain 5 to 8 data bits, the first stop bit is used to
indicate the frame type. If the Receiver is set up for frames with 9 data bits, the ninth bit is used.
When the frame type bit is one, the frame contains an address. When the frame type bit is zero,
the frame is a data frame. The Transmitter is unaffected by the MPCM setting, but if 5- to 8-bit
character frames are used, the Transmitter must be set to use two stop bit since the first stop bit
is used for indicating the frame type.
If a particular slave MCU has been addressed, it will receive the following data frames as nor-
mal, while the other slave MCUs will ignore the received frames until another address frame is
received.
For an MCU to act as a master MCU, it should use a 9-bit character frame format. The ninth bit
must be set when an address frame is being transmitted and cleared when a data frame is being
transmitted. The slave MCUs must in this case be set to use a 9-bit character frame format.
The following procedure should be used to exchange data in Multi-processor Communication
mode:
Using any of the 5- to 8-bit character frame formats is possible, but impractical since the
Receiver must change between using n and n+1 character frame formats. This makes full
duplex operation difficult since the Transmitter and Receiver uses the same character size
setting.
1. All Slave MCUs are in Multi-processor Communication mode.
2. The Master MCU sends an address frame, and all slaves receive and read this frame.
3. Each Slave MCU determines if it has been selected.
4. The addressed MCU will disable MPCM and receive all data frames. The other slave
5. When the addressed MCU has received the last data frame, it must enable MPCM
MCUs will ignore the data frames.
again and wait for new address frame from the Master. The process then repeats from
2.
USART
XCK
RxD
TxD
N/A
Comparison of USART in Master SPI mode and SPI pins.
MOSI
MISO
SCK
SPI
SS
Comment
Master Out only
Master In only
Functionally identical
Not supported by USART in Master SPI
Table
XMEGA A
21-5.
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