ATXMEGA256A3B-MH Atmel, ATXMEGA256A3B-MH Datasheet - Page 368

• Manufacturer Part Number: ATXMEGA256A3B-MH
• Description: MCU AVR 256KB FLASH A3B 64-QFN
• Manufacturer: Atmel
• Series: AVR® XMEGAr

Specifications of ATXMEGA256A3B-MH

• Core Processor: AVR
• Core Size: 8/16-Bit
• Speed: 32MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 49
• Program Memory Size: 256KB (128K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 3.6 V
• Data Converters: A/D 16x12b; D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-MLF®, 64-QFN
• Processor Series: ATXMEGA256x
• Core: AVR8
• Data Bus Width: 8 bit, 16 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, SPI, USART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 49
• Number Of Timers: 7
• Operating Supply Voltage: 1.6 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• On-chip Dac: 12 bit, 2 Channel
• For Use With: ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATSTK600 - DEV KIT FOR AVR/AVR32770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPI
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ATXMEGA256A3B-MU; ATXMEGA256A3B-MU

30.11.1.2
8077H–AVR–12/09
Addressing the Flash
Figure 30-1. Read-While-Write vs. No Read-While-Write
The Z-pointer is used to hold the Flash memory address for read and write access. The Z pointer
consists of the ZL and ZH registers in the register file, and RAMPZ Register for devices with
more than 64K bytes for Flash memory. For more details on the Z-pointer refer to
and Z- Registers” on page
Since the Flash is word accessed and organized in pages, the Z-pointer can be treated as hav-
ing two sections. The least significant bits address the words within a page, while the most
significant bits address the page within the Flash. This is shown in
word address in the page (FWORD) is held by the bits [WORDMSB:1] in the Z-pointer. The
remaining bits [PAGEMSB:WORDMSB+1] in the Z-pointer holds the Flash page address
(FPAGE). Together FWORD and FPAGE holds an absolute address to a word in the Flash.
For Flash read operations (ELPM and LMP), one byte is read at a time. For this the Least Signif-
icant Bit (bit 0) in the Z-pointer is used to select the low byte or high byte in the word address. If
this bit is 0, the low byte is read, and if this bit is 1 the high byte is read.
The size of FWORD and FPAGE will depend on the page and flash size in the device, refer to
each device data sheet for details on this.
Once a programming operation is initiated, the address is latched and the Z-pointer can be
updated and used for other operations.
Z-pointer
Adresses RWW
Section
Code Located in
NRWW Section Can
be Read During the
Operation
10.
Boot Loader Section -
No Read-While-Write
Application Section -
Read-While-Write
(NRWW)
(RWW)
Figure 30-2 on page
Z-pointer
Adresses NRWW
Section
CPU is Halted
During the Operation
XMEGA A
”The X-, Y-
369. The
368