ATXMEGA256A3B-MH Atmel, ATXMEGA256A3B-MH Datasheet - Page 180

• Manufacturer Part Number: ATXMEGA256A3B-MH
• Description: MCU AVR 256KB FLASH A3B 64-QFN
• Manufacturer: Atmel
• Series: AVR® XMEGAr

Specifications of ATXMEGA256A3B-MH

• Core Processor: AVR
• Core Size: 8/16-Bit
• Speed: 32MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 49
• Program Memory Size: 256KB (128K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 3.6 V
• Data Converters: A/D 16x12b; D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-MLF®, 64-QFN
• Processor Series: ATXMEGA256x
• Core: AVR8
• Data Bus Width: 8 bit, 16 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, SPI, USART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 49
• Number Of Timers: 7
• Operating Supply Voltage: 1.6 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• On-chip Dac: 12 bit, 2 Channel
• For Use With: ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATSTK600 - DEV KIT FOR AVR/AVR32770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPI
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ATXMEGA256A3B-MU; ATXMEGA256A3B-MU

15.5
8077H–AVR–12/09
Pattern Generation
Figure 15-4. Dead Time Generator timing diagram
The pattern generator extension reuses the DTI registers to produce a synchronized bit pattern
on the port it is connected to. In addition, the waveform generator output from CC channel A
(CCA)) can be distributed to and override all the port pins. These features are primarily intended
for handling the commutation sequence in BLDC and Stepper Motor Applications.
Figure 15-5. Pattern Generator block diagram
A block diagram of the pattern generator is shown in
where the corresponding OOE bit is set the multiplexer will output the waveform from CCA.
As for all other types of the Timer/Counter double-buffered registers the register update is syn-
chronized to the UPDATE condition set by the waveform generation mode. If the
synchronization provided is not required by the application, the application code can simply
access the DTIOE and PORTx registers directly.
The pins direction must be set for any output from the pattern generator to be visible on the port.
"WG output"
"dtls"
"dths"
"dti_cnt"
UPDATE
V
EN
DTIOE[7:0]
DTIBLS
t
DTILS
t
P
Timer/Counter 0 (TCx0)
V
EN
t
T
DTIHS
Figure 15-5 on page
PORTx[7:0]
DTIBHS
Px[7:0]
180. For each port pin
CCA WG output
XMEGA A
Expand
1 to 8
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