ATXMEGA256A3B-MH Atmel, ATXMEGA256A3B-MH Datasheet - Page 263

• Manufacturer Part Number: ATXMEGA256A3B-MH
• Description: MCU AVR 256KB FLASH A3B 64-QFN
• Manufacturer: Atmel
• Series: AVR® XMEGAr

Specifications of ATXMEGA256A3B-MH

• Core Processor: AVR
• Core Size: 8/16-Bit
• Speed: 32MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 49
• Program Memory Size: 256KB (128K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 3.6 V
• Data Converters: A/D 16x12b; D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-MLF®, 64-QFN
• Processor Series: ATXMEGA256x
• Core: AVR8
• Data Bus Width: 8 bit, 16 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, SPI, USART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 49
• Number Of Timers: 7
• Operating Supply Voltage: 1.6 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• On-chip Dac: 12 bit, 2 Channel
• For Use With: ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATSTK600 - DEV KIT FOR AVR/AVR32770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPI
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ATXMEGA256A3B-MU; ATXMEGA256A3B-MU

23.4.2
8077H–AVR–12/09
DMA Support
The State memory contains the AES State throughout the encryption/decryption process. The
initial value of the State is the initial data (i.e. plain text in the encryption mode, and cipher text in
the decryption mode). The last value of the State is the encrypted/decrypted data.
Figure 23-3. The Key memory with pointers and register.
In the AES Crypto Module the following definition of the Key is used:
In decryption mode the Key Expansion procedure must be executed by software before opera-
tion with the AES Crypto Module, so that the last subkey is ready to be loaded through the Key
register. Alternatively this procedure can be run by hardware by using the AES Crypto Module
and process a dummy data block in encryption mode, using the same Key. After the end of the
encryption, reading from the Key memory allows to obtain the last subkey, i.e. get the result of
the Key Expansion procedure.
depending on the mode (encryption or decryption) and status of the AES Crypto Module.
Table 23-1.
The AES module can trigger a DMA transfer when encryption/decryption procedure is complete.
Fore more details on DMA transfer triggers, refer to
• In encryption mode, the Key is the one defined in the AES standard.
• In decryption mode, the Key is the last subkey of the Expanded Key defined in the AES
Same key as loaded
standard.
Before data
processing
The result of reading the Key memory at different stages.
address pointer
access to CTRL
4-bit key write
Reset pointer
Encryption
reset or
generated from the
The last subkey
processing
loaded key
After data
Table 23-1 on page 263
KEY
14
15
0
1
-
Same key as loaded
Section 5.4 ”Transfer Triggers” on page
Before data
processing
shows the results of reading the key,
address pointer
Decryption
access to CTRL
4-bit key read
Reset pointer
reset or
generated form the last
XMEGA A
loaded subkey.
The initial key
processing
After data
263
50.