ATXMEGA256A3B-MH Atmel, ATXMEGA256A3B-MH Datasheet - Page 374

• Manufacturer Part Number: ATXMEGA256A3B-MH
• Description: MCU AVR 256KB FLASH A3B 64-QFN
• Manufacturer: Atmel
• Series: AVR® XMEGAr

Specifications of ATXMEGA256A3B-MH

• Core Processor: AVR
• Core Size: 8/16-Bit
• Speed: 32MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 49
• Program Memory Size: 256KB (128K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 3.6 V
• Data Converters: A/D 16x12b; D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-MLF®, 64-QFN
• Processor Series: ATXMEGA256x
• Core: AVR8
• Data Bus Width: 8 bit, 16 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, SPI, USART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 49
• Number Of Timers: 7
• Operating Supply Voltage: 1.6 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• On-chip Dac: 12 bit, 2 Channel
• For Use With: ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATSTK600 - DEV KIT FOR AVR/AVR32770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPI
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ATXMEGA256A3B-MU; ATXMEGA256A3B-MU

30.11.2.14
30.11.3
Table 30-3.
30.11.3.1
30.11.3.2
8077H–AVR–12/09
CMD[6:0]
0x00
Fuses and Lock Bits
0x07
0x08
NVM Fuse and Lock Bit Commands
Group Configuration
NO_OPERATION
READ_FUSES
WRITE_LOCK_BITS
Read User Signature Row / Calibration Row
Write Lock Bits Write
Read Fuses
Fuse and Lock Bit Commands
The Read User Signature Row and Red Calibration Row commands are used to read one byte
from the User Signature Row or Calibration Row.
The destination register will be loaded during the execution of the LPM instruction.
The NVM Flash commands that can be used for accessing the Fuses and Lock Bits are listed in
Table
For self-programming of the Fuses and Lock Bits, the Trigger for Action Triggered Commands is
to set the CMDEX bit in the NVM CTRLA register (CMDEX). The Read Triggered Commands
are triggered by executing the (E)LPM instruction (LPM). The Write Triggered Commands is trig-
gered by a executing the SPM instruction (SPM).
The Change Protected column indicate if the trigger is protected by the Configuration Change
Protection (CCP) during self-programming. The two last columns shows the address pointer
used for addressing, and the source/destination data register.
Section 30.11.3.1 on page 374
algorithm for each NVM operation.
The Write Lock Bits command is used to program the Boot Lock Bits to a more secure settings
from software.
1.
2.
3.
during self-programming.
The BUSY flag in the NVM STATUS register will be set until the command is finished. The CPU
is halted during the complete execution of the command.
This command can be executed from both the Boot Loader Section and the Application Section.
The EEPROM and Flash Page Buffer is automatically erased when the Lock Bits are written.
The Read Fuses command is used to read the Fuses from software.
1. Load the Z-pointer with the byte address to read.
2. Load the NVM CMD register with the Read User Signature Row / Calibration Row
3. Execute the LPM instruction.
command
Load the NVM DATA0 register with the new Lock bit value.
Load the NVM CMD register with the Write Lock Bit command.
Set the CMDEX bit in the NVM CTRLA register. This requires the timed CCP sequence
30-3.
Description
No Operation
Read Fuses
Write Lock Bits
through
Trigger
CMDEX
CMDEX
-
Section 30.11.3.2 on page 374
CPU
Halted
N
N
-
Change
Protected
N
Y
-
Address
pointer
ADDR
ADDR
-
explain in details the
XMEGA A
Data
register
DATA
-
-
NVM
Busy
Y
Y
-
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