ATXMEGA256A3B-MH Atmel, ATXMEGA256A3B-MH Datasheet - Page 435

• Manufacturer Part Number: ATXMEGA256A3B-MH
• Description: MCU AVR 256KB FLASH A3B 64-QFN
• Manufacturer: Atmel
• Series: AVR® XMEGAr

Specifications of ATXMEGA256A3B-MH

• Core Processor: AVR
• Core Size: 8/16-Bit
• Speed: 32MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 49
• Program Memory Size: 256KB (128K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 3.6 V
• Data Converters: A/D 16x12b; D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-MLF®, 64-QFN
• Processor Series: ATXMEGA256x
• Core: AVR8
• Data Bus Width: 8 bit, 16 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, SPI, USART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 49
• Number Of Timers: 7
• Operating Supply Voltage: 1.6 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• On-chip Dac: 12 bit, 2 Channel
• For Use With: ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATSTK600 - DEV KIT FOR AVR/AVR32770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPI
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ATXMEGA256A3B-MU; ATXMEGA256A3B-MU

8077H–AVR–12/09
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DMA - Direct Memory Access Controller ............................................. 49
Event System ......................................................................................... 65
4.11
4.12
4.13
4.14
4.15
4.16
4.17
4.18
4.19
4.20
4.21
4.22
4.23
4.24
4.25
4.26
5.1
5.2
5.3
5.4
5.5
5.6
5.7
5.8
5.9
5.10
5.11
5.12
5.13
5.14
5.15
5.16
5.17
Memory Timing ................................................................................................24
Device ID .........................................................................................................24
JTAG Disable ..................................................................................................24
IO Memory Protection ......................................................................................25
Register Description - NVM Controller ............................................................25
Register Description – Fuses and Lockbits .....................................................30
Register Description - Production Signature Row ...........................................36
Register Description – General Purpose I/O Memory .....................................42
Register Description – External Memory .........................................................42
Register Description – MCU Control ...............................................................42
Register Summary - NVM Controller ...............................................................46
Register Summary - Fuses and Lockbits .........................................................46
Register Summary - Production Signature Row ..............................................47
Register Summary - General Purpose I/O Registers ......................................48
Register Summary - MCU Control ...................................................................48
Interrupt Vector Summary - NVM Controller ....................................................48
Features ..........................................................................................................49
Overview ..........................................................................................................49
DMA Transaction .............................................................................................50
Transfer Triggers .............................................................................................50
Addressing .......................................................................................................51
Priority Between Channels ..............................................................................51
Double Buffering ..............................................................................................51
Transfer Buffers ...............................................................................................51
Error detection .................................................................................................52
Software Reset ................................................................................................52
Protection ........................................................................................................52
Interrupts .........................................................................................................52
Register Description – DMA Controller ............................................................53
Register Description – DMA Channel ..............................................................55
Register Summary – DMA Controller ..............................................................64
Register Summary – DMA Channel ................................................................64
DMA Interrupt Vector Summary ......................................................................64
XMEGA A
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