ATXMEGA256A3B-MH Atmel, ATXMEGA256A3B-MH Datasheet - Page 22

• Manufacturer Part Number: ATXMEGA256A3B-MH
• Description: MCU AVR 256KB FLASH A3B 64-QFN
• Manufacturer: Atmel
• Series: AVR® XMEGAr

Specifications of ATXMEGA256A3B-MH

• Core Processor: AVR
• Core Size: 8/16-Bit
• Speed: 32MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 49
• Program Memory Size: 256KB (128K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 3.6 V
• Data Converters: A/D 16x12b; D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-MLF®, 64-QFN
• Processor Series: ATXMEGA256x
• Core: AVR8
• Data Bus Width: 8 bit, 16 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, SPI, USART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 49
• Number Of Timers: 7
• Operating Supply Voltage: 1.6 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• On-chip Dac: 12 bit, 2 Channel
• For Use With: ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATSTK600 - DEV KIT FOR AVR/AVR32770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPI
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ATXMEGA256A3B-MU; ATXMEGA256A3B-MU

4.5
4.6
8077H–AVR–12/09
Data Memory
Internal SRAM
The Data memory contains the I/O Memory, internal SRAM, optionally memory mapped
EEPROM and external memory if available. The data memory is organized as one continuous
memory section, as shown in
Figure 4-2.
I/O Memory, EEPROM and SRAM will always have the same start addresses for all XMEGA
devices. External Memory (if exist) will always start at the end of Internal SRAM and end at
address 0xFFFFFF.
The internal SRAM is mapped in the Data Memory space, always starting at hexadecimal
address location 0x2000. SRAM is accessed from the CPU by using the load (LD/LDS/LDD) and
store (ST/STS/STD) instructions.
Data Memory Map
Figure 4-2 on page
0xFFFFFF
Start/End
0x000000
0x001000
0x002000
Address
External Memory
Internal SRAM
Data Memory
I/O Memory
EEPROM
(Up to 4 KB)
(Up to 4 KB)
(0 to 16 MB)
22.
XMEGA A
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