ATXMEGA256A3B-MH Atmel, ATXMEGA256A3B-MH Datasheet - Page 32

• Manufacturer Part Number: ATXMEGA256A3B-MH
• Description: MCU AVR 256KB FLASH A3B 64-QFN
• Manufacturer: Atmel
• Series: AVR® XMEGAr

Specifications of ATXMEGA256A3B-MH

• Core Processor: AVR
• Core Size: 8/16-Bit
• Speed: 32MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 49
• Program Memory Size: 256KB (128K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 3.6 V
• Data Converters: A/D 16x12b; D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-MLF®, 64-QFN
• Processor Series: ATXMEGA256x
• Core: AVR8
• Data Bus Width: 8 bit, 16 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, SPI, USART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 49
• Number Of Timers: 7
• Operating Supply Voltage: 1.6 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• On-chip Dac: 12 bit, 2 Channel
• For Use With: ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATSTK600 - DEV KIT FOR AVR/AVR32770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPI
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ATXMEGA256A3B-MU; ATXMEGA256A3B-MU

4.16.5
8077H–AVR–12/09
FUSEBYTE5 - Non-Volatile Memory Fuse Byte 5
Table 4-3.
• Bit 1 - WDLOCK: Watchdog Timer lock
The WDLOCK fuse can be programmed to lock the Watchdog Timer configuration. When this
fuse is programmed the Watchdog Timer configuration cannot be changed, and the Watchdog
Timer cannot be disabled from the application software. When this fuse is programmed the
ENABLE bit in the watchdog CTRL register is automatically set at reset. The WEN bit in the
watchdog WINCTRL register is not set automatically and needs to be enabled from software.
Table 4-4.
• Bit 0 - JTAGEN: JTAG enabled
The JTAGEN fuse decides whether or not the JTAG interface is enabled.
When the JTAG interface is disabled all access through JTAG is prohibited, and the device can
only be accessed using the Program and Debug Interface (PDI).
Table 4-5.
The JTAGEN fuse is only available on devices with JTAG interface.
• Bit 7:6 - Reserved
These bits are reserved. For compatibility with future devices, always write these bits to one
when this register is written.
Bit
+0x05
Read/Write
Initial Value
STARTUPTIME[1:0]
WDLOCK
JTAGEN
00
01
10
11
0
1
0
1
Start-up Time
Watchdog Timer locking
JTAG Enable
R/W
7
1
-
Description
Watchdog Timer locked for modifications
Watchdog Timer not locked
Description
JTAG enabled
JTAG disabled
R/W
6
1
-
R
5
BODACT[1:0]
-
4
R
-
1kHz ULP oscillator Cycles
EESAVE
R/W
3
-
Reserved
64
4
0
R/W
2
-
BODLEVEL[2:0]
R/W
1
-
XMEGA A
R/W
0
-
FUSEBYTE5
32