ATXMEGA256A3B-MH Atmel, ATXMEGA256A3B-MH Datasheet - Page 271

• Manufacturer Part Number: ATXMEGA256A3B-MH
• Description: MCU AVR 256KB FLASH A3B 64-QFN
• Manufacturer: Atmel
• Series: AVR® XMEGAr

Specifications of ATXMEGA256A3B-MH

• Core Processor: AVR
• Core Size: 8/16-Bit
• Speed: 32MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 49
• Program Memory Size: 256KB (128K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 3.6 V
• Data Converters: A/D 16x12b; D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-MLF®, 64-QFN
• Processor Series: ATXMEGA256x
• Core: AVR8
• Data Bus Width: 8 bit, 16 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, SPI, USART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 49
• Number Of Timers: 7
• Operating Supply Voltage: 1.6 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• On-chip Dac: 12 bit, 2 Channel
• For Use With: ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATSTK600 - DEV KIT FOR AVR/AVR32770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPI
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ATXMEGA256A3B-MU; ATXMEGA256A3B-MU

24.6.3
24.6.4
8077H–AVR–12/09
Multiplexing address byte 0 and 2
Multiplexing address byte 0, 1and 2
Figure 24-3. Multiplexed SRAM connection using ALE1
When address byte 0 (A[7:0]) and address byte 2 (A[23:16) are multiplexed, they are output
from the same port, and the ALE2 signal from the device control the address latch.
Figure 24-4. Multiplexed SRAM connection using ALE2
When address byte 0 (A[7:0]), address byte 1 (A[15:8]) and address byte 2 (A[23:16] are multi-
plexed, they are output from the same port, and the ALE1 and ALE2 signal from the device
control the external address latches.
EBI
EBI
A[23:16]/
A[19:16]
A[15:8]/
A[15:8]
D[7:0]
D[7:0]
A[7:0]
A[7:0]
ALE1
ALE2
D
G
Q
D
G
Q
D[7:0]
A[7:0]
A[15:8]
A[19:16]
D[7:0]
A[7:0]
A[15:8]
A[23:16]
SRAM
SRAM
XMEGA A
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