ATXMEGA256A3B-MH Atmel, ATXMEGA256A3B-MH Datasheet - Page 233

• Manufacturer Part Number: ATXMEGA256A3B-MH
• Description: MCU AVR 256KB FLASH A3B 64-QFN
• Manufacturer: Atmel
• Series: AVR® XMEGAr

Specifications of ATXMEGA256A3B-MH

• Core Processor: AVR
• Core Size: 8/16-Bit
• Speed: 32MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 49
• Program Memory Size: 256KB (128K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 3.6 V
• Data Converters: A/D 16x12b; D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-MLF®, 64-QFN
• Processor Series: ATXMEGA256x
• Core: AVR8
• Data Bus Width: 8 bit, 16 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, SPI, USART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 49
• Number Of Timers: 7
• Operating Supply Voltage: 1.6 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• On-chip Dac: 12 bit, 2 Channel
• For Use With: ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATSTK600 - DEV KIT FOR AVR/AVR32770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPI
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ATXMEGA256A3B-MU; ATXMEGA256A3B-MU

20.7.2
20.7.3
8077H–AVR–12/09
INTCTRL - SPI Interrupt Control Register
STATUS - SPI Status Register
• Bits 1:0 - PRESCALER[1:0]: SPI Clock Prescaler
These two bits control the SCK rate of the device configured in a Master mode. These bits have
no effect in Slave mode. The relationship between SCK and the Peripheral Clock frequency (clk-
PER
Table 20-4.
• Bits 7:2 - Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always
write these bits to zero when this register is written.
• Bits 1:0 - INTLVL[1:0]: SPI Interrupt Level
These bits enable the SPI Interrupt and select the interrupt level as described in
”Interrupts and Programmable Multi-level Interrupt Controller” on page
rupt will be triggered when the IF in the STATUS register is set.
• Bit 7 - IF: SPI Interrupt Flag
When a serial transfer is complete and one byte is completely shifted in/out of the DATA regis-
ter, the IF bit is set. If SS is an input and is driven low when the SPI is in Master mode, this will
also set the IF bit. The IF is cleared by hardware when executing the corresponding interrupt
handling vector. Alternatively, the SPIF bit can be cleared by first reading the STATUS register
with IF set, and then access the DATA register.
Bit
+0x01
Read/Write
Initial Value
Bit
+0x02
Read/Write
Initial Value
)is shown in
CLK2X
0
0
0
0
1
1
1
1
SPIF
7
R
0
R
-
7
0
Relationship Between SCK and the Peripheral Clock (clk
Table 20-4 on page
WCOL
6
R
0
R
6
0
-
PRESCALER[1:0]
R
R
5
0
5
0
-
-
00
01
10
11
00
01
10
11
233.
R
R
4
0
4
0
-
-
R
R
3
0
3
0
SCK Frequency
clk
clk
clk
clk
clk
clk
clk
clk
-
-
PER
PER
PER
PER
PER
PER
PER
PER
/4
/16
/64
/128
/2
/8
/32
/64
R
R
2
0
2
0
-
-
R/W
PER
R
1
0
1
0
-
123. The enabled inter-
INTLVL[1:0]
) frequency
XMEGA A
R/W
R/W
0
0
0
0
-
Section 12.
INTCTRL
STATUS
233