ATXMEGA256A3B-MH Atmel, ATXMEGA256A3B-MH Datasheet - Page 311

• Manufacturer Part Number: ATXMEGA256A3B-MH
• Description: MCU AVR 256KB FLASH A3B 64-QFN
• Manufacturer: Atmel
• Series: AVR® XMEGAr

Specifications of ATXMEGA256A3B-MH

• Core Processor: AVR
• Core Size: 8/16-Bit
• Speed: 32MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 49
• Program Memory Size: 256KB (128K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 3.6 V
• Data Converters: A/D 16x12b; D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-MLF®, 64-QFN
• Processor Series: ATXMEGA256x
• Core: AVR8
• Data Bus Width: 8 bit, 16 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, SPI, USART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 49
• Number Of Timers: 7
• Operating Supply Voltage: 1.6 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• On-chip Dac: 12 bit, 2 Channel
• For Use With: ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATSTK600 - DEV KIT FOR AVR/AVR32770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPI
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ATXMEGA256A3B-MU; ATXMEGA256A3B-MU

8077H–AVR–12/09
• Bit 7 - Reserved
This bit is unused and reserved for future use. For compatibility with future devices, always write
this bit to zero when this register is written.
• Bits 6:3 - MUXPOS[3:0]: MUX selection on Positive ADC input
These bits define the MUX selection for the positive ADC input.
Table 25-12 on page 311
Table 25-11. ADC MUXPOS Configuration when INPUTMODE[1:0] = 00 (Internal) is used
Table 25-12. ADC MUXPOS Configuration when INPUTMODE[1:0] = 01 (Single-ended),
For devices with more then 8 inputs into an ADC multiplexer, the MUXPOS3 bit is used to select
ADC channels 8 (ADC8) and above.
• Bits 2 - Reserved
This bit is unused and reserved for future use. For compatibility with future devices, always write
this bit to zero when this register is written.
• Bits 1:0 - MUXNEG[1:0]: MUX selection on Negative ADC input
These bits define the MUX selection for the negative ADC input when differential measurements
are done. For internal or single-ended measurements, these bits are not in use.
Table 25-13 on page 312 andTable 25-14 on page 312
MUXPOS[2:0]
MUXPOS[2:0]
000
001
010
011
100
101
110
111
000
001
010
011
100
101
110
111
INPUTMODE[1:0] = 10 (Differential) or INPUTPMODE[1:0] = 1 (Differential with
gain) is used.
shows the possible input selection for the different input modes.
Group Configuration
Group Configuration
SCALEDVCC
BANDGAP
TEMP
PIN0
PIN1
PIN2
PIN3
PIN4
PIN5
PIN6
PIN7
DAC
shows the possible input sections.
Temperature Reference.
Bandgap voltage
1/10 scaled V
Table 25-11 on page 311
Analog input
Analog input
DAC output
Reserved
Reserved
Reserved
Reserved
ADC0 pin
ADC1 pin
ADC2 pin
ADC3 pin
ADC4 pin
ADC5 pin
ADC6 pin
ADC7 pin
XMEGA A
CC
and
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