ATXMEGA256A3B-MH Atmel, ATXMEGA256A3B-MH Datasheet - Page 143

• Manufacturer Part Number: ATXMEGA256A3B-MH
• Description: MCU AVR 256KB FLASH A3B 64-QFN
• Manufacturer: Atmel
• Series: AVR® XMEGAr

Specifications of ATXMEGA256A3B-MH

• Core Processor: AVR
• Core Size: 8/16-Bit
• Speed: 32MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 49
• Program Memory Size: 256KB (128K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 3.6 V
• Data Converters: A/D 16x12b; D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-MLF®, 64-QFN
• Processor Series: ATXMEGA256x
• Core: AVR8
• Data Bus Width: 8 bit, 16 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, SPI, USART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 49
• Number Of Timers: 7
• Operating Supply Voltage: 1.6 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• On-chip Dac: 12 bit, 2 Channel
• For Use With: ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATSTK600 - DEV KIT FOR AVR/AVR32770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPI
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ATXMEGA256A3B-MU; ATXMEGA256A3B-MU

13.15 Register Description – Multiport Configuration
13.15.1
13.15.2
8077H–AVR–12/09
MPCMASK - Multi-pin Configuration Mask Register
VPCTRLA - Virtual Port-map Control Register A
• Bit 2:0 - ISC[2:0]: Input/Sense Configuration
These bits set the input and sense configuration on pin n according to
configuration decides how the pin can trigger port interrupts and events. When the input buffer is
not disabled, the schmitt triggered input is sampled (synchronized) and can be read in the IN
register.
Table 13-5.
Note:
• Bit 7:0 - MPCMASK[7:0]: Multi-pin Configuration Mask
The MPCMASK register enables several pins in a port to be configured at the same time. Writing
a one to bit n allows that pin to be part of the multi-pin configuration. When a pin configuration is
written to one of the PINnCTRL registers of the port, that value is written to all the PINnCTRL
registers of the pins matching the bit pattern in the MPCMASK register for that port. It is not nec-
essary to write to one of the registers that is set by the MPCMASK register. The MPCMASK
register is automatically cleared after any PINnCTRL registers is written.
Bit
+0x00
Read/Write
Initial Value
Bit
+0x02
Read/Write
Initial Value
ISC[2:0]
000
001
010
011
100
101
110
111
1. A low pin value will not generate events, and a high pin value will continuously generate
2. Only Port A - F supports the input buffer disable option.
events.
R/W
R/W
7
0
7
0
Input/Sense Configuration
Group Configuration
BOTHEDGES
RISING
FALLING
LEVEL
INTPUT_DISABLE
R/W
R/W
6
0
6
0
VP1MAP[3:0]
R/W
R/W
5
0
5
0
R/W
R/W
4
0
4
0
MPCMASK[7:0]
Sense both edges
Sense rising edge
Sense falling edge
Sense low level
Reserved
Reserved
Reserved
Input buffer disabled
R/W
R/W
3
0
3
0
(1)
R/W
R/W
2
0
2
0
VP0MAP[3:0]
(2)
Description
R/W
R/W
1
0
1
0
Table
XMEGA A
13-5. The sense
R/W
R/W
0
0
0
0
MPCMASK
VPCTRLA
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