ATXMEGA256A3B-MH Atmel, ATXMEGA256A3B-MH Datasheet - Page 12

• Manufacturer Part Number: ATXMEGA256A3B-MH
• Description: MCU AVR 256KB FLASH A3B 64-QFN
• Manufacturer: Atmel
• Series: AVR® XMEGAr

Specifications of ATXMEGA256A3B-MH

• Core Processor: AVR
• Core Size: 8/16-Bit
• Speed: 32MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 49
• Program Memory Size: 256KB (128K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 3.6 V
• Data Converters: A/D 16x12b; D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-MLF®, 64-QFN
• Processor Series: ATXMEGA256x
• Core: AVR8
• Data Bus Width: 8 bit, 16 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, SPI, USART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 49
• Number Of Timers: 7
• Operating Supply Voltage: 1.6 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• On-chip Dac: 12 bit, 2 Channel
• For Use With: ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATSTK600 - DEV KIT FOR AVR/AVR32770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPI
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ATXMEGA256A3B-MU; ATXMEGA256A3B-MU

3.11
3.11.1
3.12
3.12.1
8077H–AVR–12/09
Accessing 16-bits Registers
Configuration Change Protection
Accessing 24- and 32-bit Registers
Sequence for write operation to protected I/O registers
The AVR data bus is 8-bit so accessing 16-bit registers requires atomic operations. These regis-
ters must be byte-accessed using two read or write operations. When reading the high byte is
buffered and when writing the low byte will be buffered. A 16-bit register is connected to the 8-bit
bus and a temporary register using a 16-bit bus. This ensures that the low- and high-byte of 16-
bit registers is always accessed simultaneously when reading or writing the register.
For a write operation, the low-byte of the 16-bit register must be written before the high-byte.
The low-byte is then written into the temporary register. When the high-byte of the 16-bit register
is written, the temporary register is copied into the low-byte of the 16-bit register in the same
clock cycle.
For a read operation, the low-byte of the 16-bit register must be read before the high-byte. When
the low byte register is read by the CPU, the high byte of the 16-bit register is copied into the
temporary register in the same clock cycle as the low byte is read. When the high-byte is read, it
is then read from the temporary register.
Interrupts can corrupt the timed sequence if the interrupt is triggered and try to access the same
16-bit register during an atomic 16-bit read/write operations. To prevent this, interrupts can be
disabled when writing or reading 16-bit registers.
The temporary registers can also be read and written directly from user software.
For 24- and 32-bit registers the read and write access is done in the same way as described for
16-bit registers, except there are two temporary registers for 24-bit register and three for 32-bit
registers. The least significant byte must be written first when doing a write, and read first when
doing a read.
System critical I/O register settings are protected from accidental modification. The SPM instruc-
tion is protected from accidental execution, and the LPM instruction is protected when reading
the fuses and signature row. This is handled globally by the Configuration Change Protection
(CCP) register. Changes to the protected I/O registers or bit, or execution of the protected
instructions are only possible after the CPU writes a signature to the CCP register. The different
signatures is described the register description.
There are 2 mode of operation, one for protected I/O registers and one for protected SPM/LPM.
1. The application code writes the signature for change enable of protected I/O registers
2. Within 4 instruction cycles, the application code must write the appropriate data to the
to the CCP register.
protected register. Most protected registers also contain a write enable/change enable
bit. This bit must be written to one in the same operation as the data is written. The pro-
tected change is immediately disabled if the CPU performs write operations to the I/O
register or data memory, or if the instruction SPM, LPM or SLEEP is executed.
XMEGA A
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