ATXMEGA256A3B-MH Atmel, ATXMEGA256A3B-MH Datasheet - Page 440

• Manufacturer Part Number: ATXMEGA256A3B-MH
• Description: MCU AVR 256KB FLASH A3B 64-QFN
• Manufacturer: Atmel
• Series: AVR® XMEGAr

Specifications of ATXMEGA256A3B-MH

• Core Processor: AVR
• Core Size: 8/16-Bit
• Speed: 32MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 49
• Program Memory Size: 256KB (128K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 3.6 V
• Data Converters: A/D 16x12b; D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-MLF®, 64-QFN
• Processor Series: ATXMEGA256x
• Core: AVR8
• Data Bus Width: 8 bit, 16 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, SPI, USART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 49
• Number Of Timers: 7
• Operating Supply Voltage: 1.6 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• On-chip Dac: 12 bit, 2 Channel
• For Use With: ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATSTK600 - DEV KIT FOR AVR/AVR32770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPI
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ATXMEGA256A3B-MU; ATXMEGA256A3B-MU

8077H–AVR–12/09
20 SPI – Serial Peripheral Interface ......................................................... 229
21 USART ................................................................................................... 235
22 IRCOM - IR Communication Module .................................................. 256
19.10
19.11
19.12
19.13
19.14
20.1
20.2
20.3
20.4
20.5
20.6
20.7
20.8
20.9
21.1
21.2
21.3
21.4
21.5
21.6
21.7
21.8
21.9
21.10
21.11
21.12
21.13
21.14
21.15
21.16
21.17
22.1
Register Description - TWI Slave ..................................................................223
Register Summary - TWI ...............................................................................228
Register Summary - TWI Master ...................................................................228
Register Summary - TWI Slave .....................................................................228
Interrupt Vector Summary .............................................................................228
Features ........................................................................................................229
Overview ........................................................................................................229
Master Mode ..................................................................................................230
Slave Mode ....................................................................................................230
Data Modes ...................................................................................................231
DMA Support .................................................................................................232
Register Description ......................................................................................232
Register Summary .........................................................................................234
SPI Interrupt vectors ......................................................................................234
Features ........................................................................................................235
Overview ........................................................................................................235
Clock Generation ...........................................................................................237
Frame Formats ..............................................................................................240
USART Initialization .......................................................................................241
Data Transmission - The USART Transmitter ...............................................241
Data Reception - The USART Receiver ........................................................242
Asynchronous Data Reception ......................................................................243
The Impact of Fractional Baud Rate Generation ...........................................246
USART in Master SPI Mode ..........................................................................247
USART SPI vs. SPI .......................................................................................247
Multi-processor Communication Mode ..........................................................248
IRCOM Mode of Operation ............................................................................249
DMA Support .................................................................................................249
Register Description ......................................................................................249
Register Summary .........................................................................................255
Interrupt Vector Summary .............................................................................255
Features ........................................................................................................256
XMEGA A
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