ATXMEGA256A3B-MH Atmel, ATXMEGA256A3B-MH Datasheet - Page 341

• Manufacturer Part Number: ATXMEGA256A3B-MH
• Description: MCU AVR 256KB FLASH A3B 64-QFN
• Manufacturer: Atmel
• Series: AVR® XMEGAr

Specifications of ATXMEGA256A3B-MH

• Core Processor: AVR
• Core Size: 8/16-Bit
• Speed: 32MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 49
• Program Memory Size: 256KB (128K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 3.6 V
• Data Converters: A/D 16x12b; D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-MLF®, 64-QFN
• Processor Series: ATXMEGA256x
• Core: AVR8
• Data Bus Width: 8 bit, 16 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, SPI, USART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 49
• Number Of Timers: 7
• Operating Supply Voltage: 1.6 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• On-chip Dac: 12 bit, 2 Channel
• For Use With: ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATSTK600 - DEV KIT FOR AVR/AVR32770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPI
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ATXMEGA256A3B-MU; ATXMEGA256A3B-MU

28.4.7
28.5
Figure 28-2. JTAG data register overview
28.5.1
8077H–AVR–12/09
Data registers
PDICOM; 0x7
Bypass register
D
D
D
D
D
D
D
D
D
I/O P O R T S
D
P D I
PDICO is an AVR specific instruction and using the JTAG TAP as an alternative interface
towards the PDI (Programming and Debug Interface).
The active states are:
The supported data registers that can be connected between TDI and TDO are:
The Bypass Register consists of a single Shift Register stage. When the Bypass Register is
selected as path between TDI and TDO, the register is reset to 0 when leaving the Capture-DR
controller state. The Bypass Register can be used to shorten the scan chain on a system when
the other devices are to be tested.
D
• Capture-DR: Loads a logical "0" into the Bypass Register.
• Shift-DR: The Bypass Register cell between TDI and TDO is shifted.
• Capture-DR: Parallel data from the PDI is sampled into the PDICOM data register.
• Shift-DR: The PDICOM data register is shifted by the TCK input.
• Update-DR: Commands or operands are parallel-latched from the PDICOM data register into
• Bypass register (Ref: register A in
• Device Identification register (Ref: registers C in
• Boundary-scan chain (Ref: register D in
• PDICOM data register (Ref: register B in
the PDI.
J T A G
A
B
C
In te rn a l re g is te rs
B
C
Figure 28-2 on page
C
Figure 28-2 on page
Figure 28-2 on page
B
C T R L
T A P
C
Figure 28-2 on page
341).
341).
341)
to a ll T C K
re g is te rs
341).
XMEGA A
T M S
T C K
T D O
T D I
341