ATXMEGA256A3B-MH Atmel, ATXMEGA256A3B-MH Datasheet - Page 152

• Manufacturer Part Number: ATXMEGA256A3B-MH
• Description: MCU AVR 256KB FLASH A3B 64-QFN
• Manufacturer: Atmel
• Series: AVR® XMEGAr

Specifications of ATXMEGA256A3B-MH

• Core Processor: AVR
• Core Size: 8/16-Bit
• Speed: 32MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 49
• Program Memory Size: 256KB (128K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 3.6 V
• Data Converters: A/D 16x12b; D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-MLF®, 64-QFN
• Processor Series: ATXMEGA256x
• Core: AVR8
• Data Bus Width: 8 bit, 16 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, SPI, USART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 49
• Number Of Timers: 7
• Operating Supply Voltage: 1.6 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• On-chip Dac: 12 bit, 2 Channel
• For Use With: ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATSTK600 - DEV KIT FOR AVR/AVR32770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPI
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ATXMEGA256A3B-MU; ATXMEGA256A3B-MU

8077H–AVR–12/09
Figure 14-2. Timer/Counter Block Diagram
The Counter Register (CNT), the Period Registers w/buffer (PER and PERBUF), and the com-
pare and Capture registers w/buffers (CCx and CCxBUF) are 16-bit registers.
During normal operation the counter value is continuously compared to zero and the period
(PER) value to determine whether the counter has reached TOP or BOTTOM.
The counter value is also compared to the CCx registers. These comparators can be used to
generate interrupt requests or request DMA transactions. They also generate events for the
Event System. The waveform generator modes use the comparators to set the waveform period
or pulse width.
A prescaled peripheral clock and events from the Event System can be used for controlling the
counter. The Event System is also used as source to the input capture. Combined with the
Quadrature Decoding functionality in the Event System QDEC, the Timer/Counter can be used
for high speed Quadrature Decoding.
Bus Bridge
Base Counter
Compare/Capture
(x = {A,B,C,D})
Counter
V
V
TEMP
PERBUF
CCxBUF
PER
CNT
CCx
A
=
I/O Data Bus (8-bit)
B
= 0
C
CTRL
D
=
Clock Select
Event Select
E
CKSEL
EVSEL
"count"
"clear"
"load"
"direction"
"capture"
"match"
TOP
BOTTOM
G
Control Logic
Control Logic
INTCTRL
Generation
Waveform
A
B
INTFLAGS
XMEGA A
OVF/UNF
(INT/DMA Req.)
ERRIF
(INT Req.)
OCx Out
CCxIF
(INT/DMA
Req.)
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