ATXMEGA256A3B-MH Atmel, ATXMEGA256A3B-MH Datasheet - Page 56

• Manufacturer Part Number: ATXMEGA256A3B-MH
• Description: MCU AVR 256KB FLASH A3B 64-QFN
• Manufacturer: Atmel
• Series: AVR® XMEGAr

Specifications of ATXMEGA256A3B-MH

• Core Processor: AVR
• Core Size: 8/16-Bit
• Speed: 32MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 49
• Program Memory Size: 256KB (128K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 3.6 V
• Data Converters: A/D 16x12b; D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-MLF®, 64-QFN
• Processor Series: ATXMEGA256x
• Core: AVR8
• Data Bus Width: 8 bit, 16 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, SPI, USART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 49
• Number Of Timers: 7
• Operating Supply Voltage: 1.6 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• On-chip Dac: 12 bit, 2 Channel
• For Use With: ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATSTK600 - DEV KIT FOR AVR/AVR32770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPI
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ATXMEGA256A3B-MU; ATXMEGA256A3B-MU

5.14.2
8077H–AVR–12/09
CTRLB - DMA Channel Control Register B
• Bit 2 - SINGLE: DMA Channel Single Shot Data transfer
Setting this bit enables the single shot mode. The channel will then do a burst transfer of
BURSTLEN bytes on the transfer trigger. This bit can not be changed if the channel is busy.
• Bit 1:0 - BURSTLEN[1:0]: DMA Channel Burst Mode
These bits decide the DMA channel burst mode according to
can not be changed if the channel is busy.
Table 5-3.
• Bit 7- CHBUSY - DMA Channel Busy
When the DMA Channel starts a DMA transaction, the CHBUSY flag will be read as one. This
flag is automatically cleared when the DMA channel is disabled, when the Channel Transaction
Complete Interrupt Flag is set or if the Channel Error Interrupt flag is set.
• Bit 6 - CHPEND - DMA Channel Pending
If a block transfer is pending on the DMA channel, the CHPEND flag will be read as one. This
flag is automatically cleared when the transfer starts, or if the transfer is aborted
• Bit 5 - ERRIF - DMA Channel Error Interrupt Flag
If an error condition is detected the DMA channel the ERRIF flag will be set, and the optional
interrupt is generated. Since the DMA Channel Error Interrupt share interrupt address with DMA
Channel Transaction Complete, the ERRIF will not be cleared when the interrupt vector is exe-
cuted. This flag is cleared by writing a one to the bit location.
• Bit 4 - TRNIF - DMA Channel n Transaction Complete Interrupt Flag
When a transaction on the DMA Channel has been completed, the TRNIF flag will set, and the
optional interrupt is generated. When repeat is not enabled the transaction is complete and the
TRNIFR is set after the block transfer. When unlimited repeat is enabled the TRNIF is also set
after each block transfer.
Since the DMA Channel Transaction Complete Channel Error Interrupt share interrupt address
with DMA Channel Error Interrupt, the TRNIF will not be cleared when the interrupt vector is exe-
cuted. This flag is cleared by writing a one to the bit location.
Bit
+0x04
Read/Write
Initial Value
BURSTLEN[1:0]
00
01
10
11
CHBUSY
DMA channel burst mode
R
7
0
CHPEND
6
R
0
ERRIF
R/W
5
0
Group Configuration
1BYTE
2BYTE
4BYTE
8BYTE
TRNIF
R/W
4
0
R/W
ERRINTLVL[1:0]
3
0
R/W
Table 5-3 on page
2
0
Description
1 byte burst mode
2 bytes burst mode
4 bytes burst mode
8 bytes burst mode
R/W
1
TRNINTLVL[1:0]
0
XMEGA A
R/W
56. These bits
0
0
CTRLB
56