ATXMEGA256A3B-MH Atmel, ATXMEGA256A3B-MH Datasheet - Page 326

• Manufacturer Part Number: ATXMEGA256A3B-MH
• Description: MCU AVR 256KB FLASH A3B 64-QFN
• Manufacturer: Atmel
• Series: AVR® XMEGAr

Specifications of ATXMEGA256A3B-MH

• Core Processor: AVR
• Core Size: 8/16-Bit
• Speed: 32MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 49
• Program Memory Size: 256KB (128K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 3.6 V
• Data Converters: A/D 16x12b; D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-MLF®, 64-QFN
• Processor Series: ATXMEGA256x
• Core: AVR8
• Data Bus Width: 8 bit, 16 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, SPI, USART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 49
• Number Of Timers: 7
• Operating Supply Voltage: 1.6 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• On-chip Dac: 12 bit, 2 Channel
• For Use With: ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATSTK600 - DEV KIT FOR AVR/AVR32770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPI
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ATXMEGA256A3B-MU; ATXMEGA256A3B-MU

26.10.9.1
26.10.9.2
26.10.10 CH1DATAL – DAC Channel 1 Data Register Low byte
26.10.10.1
26.10.10.2
26.10.11 GAINCAL – DAC Gain Calibration Register
8077H–AVR–12/09
Right-adjusted
Left-adjusted
Right-adjusted
Left-adjusted
• Bits 7:4 - Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always
write these bits to zero when this register is written.
• Bits 3:0 - CHDATA[11:8]: DAC Conversion Data Register Channel 1, 4 MSB
These bits are the 4 MSB of the 12-bit value to convert to channel 1 in right-adjusted mode.
• Bits 7:0 - CHDATA[11:4]: DAC Conversion Data Register Channel 1, 8 MSB
These bits are the 8 MSB of the 12-bit value to convert to channel 1 in left-adjusted mode.
• Bits 7:0 - CHDATA[7:0]: DBC Conversion Data Register Channel 1, 8 LSB
These bits are the 8 lsb of the 12-bit value to convert to channel 1 in right-adjusted mode.
• Bits 7:4 - CHDATA[3:0]: DAC Conversion Data Register Channel 1, 4 LSB
These bits are the 4 lsb of the 12-bit value to convert to channel 1 in left-adjusted mode.
• Bits 3:0 - Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always
write these bits to zero when this register is written.
• Bit 7 - Reserved
This bit is unused and reserved for future use. For compatibility with future devices, always write
this bit to zero when this register is written.
Bit
+0x08
Read/Write
Initial Value
Right-adjust
Left-adjust
Right-adjust
Left-adjust
Right-adjust
Left-adjust
R
7
0
-
Bit
+0x1A
Read/Write
Read/Write
Initial Value
Initial Value
R/W
6
0
R/W
R/W
7
0
0
R/W
5
0
R/W
R/W
6
0
0
CHDATA[3:0]
R/W
4
0
R/W
R/W
GAINCAL[6:0]
5
0
0
R/W
3
0
R/W
R/W
4
0
0
CHDATA[7:0]
R/W
2
0
R/W
R
0
0
3
-
R/W
1
0
R/W
R
2
0
0
-
XMEGA A
R/W
0
0
R/W
R
1
0
0
-
GAINCAL
R/W
R
0
0
0
-
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