ATXMEGA256A3B-MH Atmel, ATXMEGA256A3B-MH Datasheet - Page 310

• Manufacturer Part Number: ATXMEGA256A3B-MH
• Description: MCU AVR 256KB FLASH A3B 64-QFN
• Manufacturer: Atmel
• Series: AVR® XMEGAr

Specifications of ATXMEGA256A3B-MH

• Core Processor: AVR
• Core Size: 8/16-Bit
• Speed: 32MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 49
• Program Memory Size: 256KB (128K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 3.6 V
• Data Converters: A/D 16x12b; D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-MLF®, 64-QFN
• Processor Series: ATXMEGA256x
• Core: AVR8
• Data Bus Width: 8 bit, 16 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, SPI, USART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 49
• Number Of Timers: 7
• Operating Supply Voltage: 1.6 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• On-chip Dac: 12 bit, 2 Channel
• For Use With: ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATSTK600 - DEV KIT FOR AVR/AVR32770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPI
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ATXMEGA256A3B-MU; ATXMEGA256A3B-MU

25.17.2
8077H–AVR–12/09
MUXCTRL - ADC Channel MUX Control registers
See
settings, see
Table 25-8.
• Bit 1:0 - INPUTMODE[1:0]: Channel Input Mode
These bits define the channel mode. This setting is independent of the ADC CONVMODE
(signed/unsigned mode) setting, but differential input mode can only be done in ADC signed
mode. In single ended input mode, the negative input to the ADC will be connected to a fixed
value both for ADC signed and unsigned mode.
Table 25-9.
Table 25-10. Channel Input Modes, CONVMODE=1 (signed mode)
The MUX register defines the input source for the channel.
Bit
+0x01
Read/Write
Initial Value
INPUTMODE[1:0]
INPUTMODE[1:0]
Table 25-6 on page 305
GAIN[2:0]
000
001
010
011
100
101
110
111
00
01
10
11
00
01
10
11
”MUXCTRL - ADC Channel MUX Control registers” on page
ADC Gain Factor
Channel Input Modes, CONVMODE=0 (unsigned mode)
R
7
0
-
R/W
6
0
Group Configuration
Group Configuration
Group Configuration
for different gain factor settings. Gain is only valid with certain MUX
SINGLEENDED
SINGLEENDED
DIFFWGAIN
INTERNAL
INTERNAL
R/W
DIFF
16X
32X
64X
5
0
1X
2X
4X
8X
MUXPOS[3:0]
R/W
4
0
R/W
Description
Internal positive input signal
Single-ended positive input signal
Reserved
Reserved
Description
Internal positive input signal
Single-ended positive input signal
Differential input signal
Differential input signal with gain
3
0
R
2
0
-
Gain factor
Reserved
R/W
16x
32x
64x
1
0
1x
2x
4x
8x
MUXNEG[1:0]
310.
XMEGA A
R/W
0
0
MUXCTRL
310