ATXMEGA256A3B-MH Atmel, ATXMEGA256A3B-MH Datasheet - Page 44

• Manufacturer Part Number: ATXMEGA256A3B-MH
• Description: MCU AVR 256KB FLASH A3B 64-QFN
• Manufacturer: Atmel
• Series: AVR® XMEGAr

Specifications of ATXMEGA256A3B-MH

• Core Processor: AVR
• Core Size: 8/16-Bit
• Speed: 32MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 49
• Program Memory Size: 256KB (128K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 3.6 V
• Data Converters: A/D 16x12b; D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-MLF®, 64-QFN
• Processor Series: ATXMEGA256x
• Core: AVR8
• Data Bus Width: 8 bit, 16 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, SPI, USART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 49
• Number Of Timers: 7
• Operating Supply Voltage: 1.6 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• On-chip Dac: 12 bit, 2 Channel
• For Use With: ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATSTK600 - DEV KIT FOR AVR/AVR32770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPI
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ATXMEGA256A3B-MU; ATXMEGA256A3B-MU

4.20.6
4.20.7
8077H–AVR–12/09
MCUCR – MCU Control Register
EVSYSLOCK – Event System Lock Register
• Bit 7:0 - JTAGUID[7:0]: JTAG User ID
The JTAGUID can be used to identify two devices with identical Device ID in a JTAG scan chain.
The JTAGUID will during reset automatically be loaded from flash and placed in these registers.
• Bit 7:1 - Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always
write these bits to zero when this register is written.
• Bit 0 - JTAGD: JTAG Disable
Setting this bit will disable the JTAG interface. This bit is protected by the Configuration Change
Protection mechanism, for details refer to
page
• Bit 7:5 - Reserved
These bits are reserved and will always be read as zero. For compatibility with future devices,
always write these bits to zero when this register is written.
• Bit 4 - EVSYS1LOCK:
Setting this bit will lock all registers in the Event System related to event channels 4 to 7 for fur-
ther modifications. The following registers in the Event System are locked: CH4MUX,
CH4CTRL, CH5MUX, CH5CTRL, CH6MUX, CH6CTRL, CH7MUX, CH7CTRL. This bit is pro-
tected by the Configuration Change Protection mechanism, for details refer to
”Configuration Change Protection” on page
• Bit 3:1 - Reserved
These bits are reserved and will always be read as zero. For compatibility with future devices,
always write these bits to zero when this register is written.
• Bit 0 - EVSYS0LOCK:
Setting this bit will lock all registers in the Event System related to event channels 0 to 3 for fur-
ther modifications. The following registers in the Event System are locked: CH0MUX,
CH0CTRL, CH1MUX, CH1CTRL, CH2MUX, CH2CTRL, CH3MUX, CH3CTRL. This bit is pro-
Bit
+0x06
Read/Write
Initial Value
Bit
+0x08
Read/Write
Initial Value
12.
7
–
R
0
R
7
0
-
R
6
–
0
R
6
0
-
R
5
–
0
R
5
0
-
EVSYS1LOCK
R/W
4
0
Section 3.12 ”Configuration Change Protection” on
R
4
0
-
12.
R
3
–
0
R
3
0
-
R
2
–
0
2
R
0
-
R
1
–
0
R
1
0
-
EVSYS0LOCK
R/W
0
0
XMEGA A
JTAGD
R/W
0
0
Section 3.12
EVSYS_LOCK
MCUCR
44