ATXMEGA256A3B-MH Atmel, ATXMEGA256A3B-MH Datasheet - Page 171

• Manufacturer Part Number: ATXMEGA256A3B-MH
• Description: MCU AVR 256KB FLASH A3B 64-QFN
• Manufacturer: Atmel
• Series: AVR® XMEGAr

Specifications of ATXMEGA256A3B-MH

• Core Processor: AVR
• Core Size: 8/16-Bit
• Speed: 32MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 49
• Program Memory Size: 256KB (128K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 3.6 V
• Data Converters: A/D 16x12b; D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-MLF®, 64-QFN
• Processor Series: ATXMEGA256x
• Core: AVR8
• Data Bus Width: 8 bit, 16 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, SPI, USART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 49
• Number Of Timers: 7
• Operating Supply Voltage: 1.6 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• On-chip Dac: 12 bit, 2 Channel
• For Use With: ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATSTK600 - DEV KIT FOR AVR/AVR32770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPI
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ATXMEGA256A3B-MU; ATXMEGA256A3B-MU

14.12.10 INTFLAGS - Interrupt Flag Register
14.12.11 TEMP - Temporary Register for 16-bit Access
8077H–AVR–12/09
• Bit 7:4 - CCxIF: Compare or Capture Channel x Interrupt Flag
The Compare or Capture Interrupt Flag (CCxIF) is set on a compare match or on an input cap-
ture event on the corresponding CC channel.
For all modes of operation except for capture the CCxIF will be set when a compare match
occurs between the count register (CNT) and the corresponding compare register (CCx). The
CCxIF is automatically cleared when the corresponding interrupt vector is executed.
For input capture operation the CCxIF will be set if the corresponding compare buffer contains
valid data (i.e. when CCxBV is set). The flag will be cleared when the CCx register is read. Exe-
cuting the Interrupt Vector will in this mode of operation not clear the flag.
The flag can also be cleared by writing a one to its bit location.
The CCxIF can be used for requesting a DMA transfer. A DMA read or write access of the corre-
sponding CCx or CCxBUF will then clear the CCxIF and releases the request.
• Bit 3:2 - Reserved
These bits are reserved and will always be read as zero. For compatibility with future devices,
always write these bits to zero when this register is written.
• Bit 1 - ERRIF: Error Interrupt Flag
The ERRIF is set on multiple occasions depending on mode of operation.
In FRQ or PWM waveform generation mode of operation the ERRIF is set on a fault detect con-
dition from the fault protection feature in the AWeX Extention. For Timer/Counters which do not
have the AWeX extention available, this flag is never set in FRQ or PWM waveform generation
mode.
For capture operation the ERRIF is set if a buffer overflow occurs on any of the CC channels.
For event controlled QDEC operation the ERRIF is set when an incorrect index signal is given.
The ERRIF is automatically cleared when the corresponding interrupt vector is executed. The
flag can also be cleared by writing a one to its bit location.
• Bit 0 - OVFIF: Overflow/Underflow Interrupt Flag
The OVFIF is set either on a TOP (overflow) or BOTTOM (underflow) condition depending on
the WGMODE setting. The OVFIF is automatically cleared when the corresponding interrupt
vector is executed. The flag can also be cleared by writing a one to its bit location.
The OVFIF can also be used for requesting a DMA transfer. A DMA write access of CNT, PER,
or PERBUF will then clear the OVFIF bit.
The TEMP register is used for single cycle 16-bit access to the 16-bit Timer/Counter registers
from the CPU. The DMA controller has a separate temporary storage register. There is one com-
mon TEMP register for all the 16-bit Timer/Counter registers.
Bit
+0x0C
Read/Write
Initial Value
CCDIF
R/W
7
0
CCCIF
R/W
6
0
CCBIF
R/W
5
0
CCAIF
R/W
4
0
R
3
0
-
R
2
0
-
ERRIF
R/W
1
0
XMEGA A
OVFIF
R/W
0
0
INTFLAGS
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