ATXMEGA256A3B-MH Atmel, ATXMEGA256A3B-MH Datasheet - Page 165

• Manufacturer Part Number: ATXMEGA256A3B-MH
• Description: MCU AVR 256KB FLASH A3B 64-QFN
• Manufacturer: Atmel
• Series: AVR® XMEGAr

Specifications of ATXMEGA256A3B-MH

• Core Processor: AVR
• Core Size: 8/16-Bit
• Speed: 32MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 49
• Program Memory Size: 256KB (128K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 3.6 V
• Data Converters: A/D 16x12b; D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-MLF®, 64-QFN
• Processor Series: ATXMEGA256x
• Core: AVR8
• Data Bus Width: 8 bit, 16 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, SPI, USART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 49
• Number Of Timers: 7
• Operating Supply Voltage: 1.6 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• On-chip Dac: 12 bit, 2 Channel
• For Use With: ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATSTK600 - DEV KIT FOR AVR/AVR32770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPI
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ATXMEGA256A3B-MU; ATXMEGA256A3B-MU

14.12 Register Description
14.12.1
14.12.2
8077H–AVR–12/09
CTRLA - Control Register A
CTRLB - Control Register B
• Bit 7:4 - Reserved bits
These bits are unused and reserved for future use. For compatibility with future devices, always
write these bits to zero when this register is written.
• Bit 3:0 - CLKSEL[3:0]: Clock Select
These bits select clock source for the Timer/Counter according to
CLKSEL=0001 must be set to ensure a correct output from the waveform generator when the
Hi-Res extension is enabled.
Table 14-3.
• Bit 7:4 – CCxEN: Compare or Capture Enable
Setting these bits in FRQ or PWM waveform generation mode of operation will override of the
port output register for the corresponding OCn output pin.
When input capture operation is selected the CCxEN bits enables the capture operation for the
corresponding CC channel.
Bit
+0x01
Read/Write
Initial Value
Bit
+0x00
Read/Write
Initial Value
CLKSEL[3:0]
0000
0001
0010
0011
0100
0101
0110
0111
1xxx
CCDEN
R/W
Clock Select
7
0
R
7
0
-
Group Configuration
CCCEN
R/W
R
6
0
6
0
-
DIV1024
DIV256
EVCHn
DIV64
DIV1
DIV2
DIV4
DIV8
OFF
CCBEN
R/W
R
5
0
5
0
-
CCAEN
R/W
R
4
0
4
0
-
Description
None (i.e, Timer/Counter in ‘OFF’ state)
Prescaler: clk
Prescaler: clk/2
Prescaler: clk/4
Prescaler: clk/8
Prescaler: clk/64
Prescaler: clk/256
Prescaler: clk/1024
Event channel n, n= [0,...,7]
R/W
R
3
0
3
0
-
R/W
R/W
2
0
2
0
CLKSEL[3:0]
Table
WGMODE[2:0]
R/W
R/W
1
0
1
0
14-3.
XMEGA A
R/W
R/W
0
0
0
0
CTRLA
CTRLB
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