r5f21368sdfp Renesas Electronics Corporation., r5f21368sdfp Datasheet - Page 102

• Manufacturer Part Number: r5f21368sdfp
• Description: Renesas Mcu R8c Family / R8c/3xt-a Series
• Manufacturer: Renesas Electronics Corporation.

Under development
R8C/36T-A Group
R01UH0240EJ0001 Rev.0.01
Apr 28, 2011
8.
The watchdog timer is a function for detecting software malfunctions. Using this function is recommended, since it can
improve system reliability.
8.1
Table 8.1
Note:
Count source
Count operation
Count start condition
Count stop conditions
Watchdog timer
initialization conditions
Operation at underflow Watchdog timer interrupt or watchdog timer
Selectable functions
The watchdog timer has a 14-bit down counter and count source protection mode can be enabled or disabled.
Table 8.1 lists the Watchdog Timer Specifications.
For details on the watchdog timer reset, refer to 6.3.5 Watchdog Timer Reset.
Figure 8.1 shows the Watchdog Timer Block Diagram.
Watchdog Timer
1. Only write to the WDTR register during the refresh period when the watchdog timer is counting.
Overview
Item
Preliminary document
Specifications in this document are tentative and subject to change.
Watchdog Timer Specifications
CPU clock or low-speed on-chip oscillator
clock (1/16) for the watchdog timer
Decrement
Either of the following can be selected:
• The count is automatically started after a reset.
• The count is started by writing to the WDTS register.
• When the count source is obtained by
• When the count source is obtained by
• Reset
• 00h and then FFh are written to the WDTR register during the acceptance period
• Underflow
reset
• Prescaler division ratio
• Count source protection mode
• Start or stop of the watchdog timer after a reset
• Initial value of the watchdog timer
• Refresh acceptance period for the watchdog timer
dividing the CPU clock by 2, 16, or 128, if
the MCU enters wait mode or stop mode,
count stops.
dividing the low-speed on-chip oscillator by
16, even if the MCU enters wait mode or
stop mode, count does not stop.
(when an acceptance period is set.)
Count Source Protection Mode Disabled
Selected by bits WDTC6 and WDTC7 in the WDTC register.
- Whether count source protection mode is enabled or disabled after a reset can be
- If count source protection mode is disabled, whether count source protection mode is
Selected by the WDTON bit in the OFS register (flash memory).
Selected by bits WDTUFS0 and WDTUFS1 in the OFS2 register.
Selected by bits WDTRCS0 and WDTRCS1 in the OFS2 register.
selected by the CSPROINI bit in the OFS register (flash memory).
enabled or disabled is selected by the CSPRO bit in the CSPR register (program).
Low-speed on-chip oscillator clock for the
watchdog timer
None
Watchdog timer reset
Count Source Protection Mode Enabled
8. Watchdog Timer
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