r5f21368sdfp Renesas Electronics Corporation., r5f21368sdfp Datasheet - Page 443

• Manufacturer Part Number: r5f21368sdfp
• Description: Renesas Mcu R8c Family / R8c/3xt-a Series
• Manufacturer: Renesas Electronics Corporation.

Under development
R8C/36T-A Group
R01UH0240EJ0001 Rev.0.01
Apr 28, 2011
Figure 20.4
(1) CKPOL Bit in U2C0 Register = 0 (transmit data is output at the falling edge and receive
(2) CKPOL Bit in U2C0 Register = 1 (transmit data is output at the rising edge and receive
The above diagram applies under the following conditions:
• UFORM bit in U2C0 register = 0 (LSB first)
• U2LCH bit in U2C1 register = 0 (not inverted)
20.3.1.1
20.3.1.2
CLK2
TXD2
RXD2
CLK2
TXD2
RXD2
data is input at the rising edge of the transfer clock)
data is input at the falling edge of the transfer clock)
If communication is aborted or a communication error occurs while transmitting or receiving in clock
synchronous serial I/O mode, follow the procedures below:
(1) Set the TE bit in the U2C1 register to 0 (transmission disabled) and the RE bit to 0 (reception disabled).
(2) Set bits SMD2 to SMD0 in the U2MR register to 000b (serial interface disabled).
(3) Set bits SMD2 to SMD0 in the U2MR register to 001b (clock synchronous serial I/O mode).
(4) Set the TE bit in the U2C1 register to 1 (transmission enabled) and the RE bit to 1 (reception enabled).
The polarity of the transfer clock is selected with the CKPOL bit in the U2C0 register. Figure 20.4 shows the
Transfer Clock Polarity.
Preliminary document
Specifications in this document are tentative and subject to change.
Measure for Dealing with Communication Errors
CLK Polarity Select Function
Transfer Clock Polarity
D0
D0
D0
D0
D1
D1
D1
D1
D2
D2
D2
D2
D3
D3
D3
D3
D4
D4
D4
D4
D5
D5
D5
D5
D6
D6
D6
D6
D7
D7
D7
D7
High output from CLK2 pin
when no transfer is in progress
Low output from CLK2 pin
when no transfer is in progress
20. Serial Interface (UART2)
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