r5f21368sdfp Renesas Electronics Corporation., r5f21368sdfp Datasheet - Page 532

• Manufacturer Part Number: r5f21368sdfp
• Description: Renesas Mcu R8c Family / R8c/3xt-a Series
• Manufacturer: Renesas Electronics Corporation.

Under development
R8C/36T-A Group
R01UH0240EJ0001 Rev.0.01
Apr 28, 2011
Figure 21.24
21.4.2.5.1
During data transfer, if the 9th clock cycle falls while the TDRE bit is 1 and the TEND bit is 1, the SCL signal
is held low until transmit data is written to the transmit register. After transmit data is written, maintain the data
setup time set with the CKS3 bit after the transmit data is output to the SDA pin and release the SCL signal
(rising) (refer to Figure 21.25 Data Setup Time during Slave Transmit Operation).
The setup time is doubled when the IICTCHALF bit in the IICCR register is set to 1, and halved when the
IICTCTWI bit in the IICCR register is set to 1.
The CKS3 bit
(master output)
(master output)
SIRDR register
SISDR register
SICR1 register
SITDR register
(slave output)
(slave output)
SISR register
SISR register
TDRE bit in
TEND bit in
processing
TRS bit in
Program
SDA
SDA
SCL
SCL
Preliminary document
Specifications in this document are tentative and subject to change.
Operation Timing in Slave Transmit Mode (I
Maintaining Data Setup Time during I
Data n
0: 9 or 10 Tcyc
1: 17 to 20 Tcyc (1 Tcyc = 1/f1 (s))
A
9
b7
Data n
1
b6
2
(3) Set TEND bit to 0.
b5
3
b4
4
b3
5
b2
6
(4) Dummy read SIRDR register
2
after setting TRS bit to 0.
C bus Interface Mode) (2)
b1
2
Slave transmit mode
7
C Slave Transmit Operation
21. Clock Synchronous Serial Interface
b0
8
9
A
(5) Set TDRE bit
to 0.
Slave receive
mode
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