r5f21368sdfp Renesas Electronics Corporation., r5f21368sdfp Datasheet - Page 548

• Manufacturer Part Number: r5f21368sdfp
• Description: Renesas Mcu R8c Family / R8c/3xt-a Series
• Manufacturer: Renesas Electronics Corporation.

Under development
R8C/36T-A Group
R01UH0240EJ0001 Rev.0.01
Apr 28, 2011
21.5.3.3
• When 1 is written to the SIRST bit, bits SDAO and SCLO in the SICR2 register are set to 1.
• In master transmit mode or slave transmit mode, when 1 is written to the SIRST bit, the TDRE bit in the SISR
• While the I
• The BBSY bit is not set to 0 even if 1 is written to the SIRST bit. However, depending on the states of SCL
• While the I
• Refer to 21.4.8 Procedure for Resetting Control Block in I
register is set to 1.
bits SCP and SDAO is disabled. Thus, write 0 to the SIRST bit before writing to any of these bits.
and SDA, a stop condition (rising of SDA when SCL is high) is generated, which may set the BBSY bit to 0.
Similarly, this may also affect other bits.
However, the function to detect a start condition, stop condition, and arbitration lost continues operating.
Therefore, the values of registers SICR1, SICR2, and SISR may be updated depending on the signal input to
pins SCL and SDA.
including the above information on the control block reset operation using the SIRST bit.
Preliminary document
Specifications in this document are tentative and subject to change.
Additional Description on SIRST Bit in SICR2 Register
2
2
C bus control block is reset by the SIRST bit, writing to the BBSY bit in the SICR2 register and
C bus control block is reset by the SIRST bit, data transmission and reception are stopped.
2
C bus Interface Mode, for more details
21. Clock Synchronous Serial Interface
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