r5f21368sdfp Renesas Electronics Corporation., r5f21368sdfp Datasheet - Page 666

• Manufacturer Part Number: r5f21368sdfp
• Description: Renesas Mcu R8c Family / R8c/3xt-a Series
• Manufacturer: Renesas Electronics Corporation.

Under development
R8C/36T-A Group
R01UH0240EJ0001 Rev.0.01
Apr 28, 2011
26.5.1
26.5.2
When the FMR01 bit in the FMR0 register is set to 1 (CPU rewrite mode enabled), the MCU enters CPU
rewrite mode and software commands can be accepted. At this time, the FMR02 bit in the FMR0 register is set
to 0 so that EW0 mode is selected.
Software commands are used to control program and erase operations. The FST register can be used to confirm
whether programming or erasure has completed.
To enter erase-suspend during auto-erasure, set the FMR20 bit to 1 (erase-suspend enabled) and the FMR21 bit
to 1 (erase-suspend request). Next, verify the FST7 bit in the FST register is set to 1 (ready), then verify the
FST6 bit is set to 1 (during erase-suspend) before accessing the flash memory. When the FST6 bit is set to 0,
erasure completes.
When the FMR21 bit in the FMR2 register is set to 0 (erase restart), auto-erasure restarts. To confirm whether
auto-erasure has restarted, verify the FST7 bit in the FST register is set to 0, then verify the FST6 bit is set to 0
(other than erase-suspend).
After the FMR01 bit in the FMR0 register is set to 1 (CPU rewrite mode enabled), EW1 mode is selected by
setting the FMR02 bit to 1.
The FST register can be used to confirm whether programming and erasure has completed.
To enable the erase-suspend function during auto-erasure, execute the block erase command after setting the
FMR20 bit in the FMR2 register to 1 (suspend enabled). To enter erase-suspend while auto-erasing the user
ROM area, set the FMR22 bit in the FMR2 register to 1 (erase-suspend request enabled by interrupt request).
Also, the interrupt to enter erase-suspend must be enabled beforehand.
When an interrupt request is generated, the FMR21 bit in the FMR2 register is automatically set to 1 (erase-
suspend request) and auto-erasure suspends after td(SR-SUS). After interrupt handling completes, set the
FMR21 bit to 0 (erase restart) to restart auto-erasure.
EW0 Mode
EW1 Mode
Preliminary document
Specifications in this document are tentative and subject to change.
26. Flash Memory
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